static void dec10_reg_abs(DisasContext *dc)
{
TCGv t0;
LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst);
assert(dc->dst != 15);
t0 = tcg_temp_new();
tcg_gen_sari_tl(t0, cpu_R[dc->src], 31);
tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0);
tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
tcg_temp_free(t0);
}
static void dec_sr(DisasContext *dc)
{
if (dc->format == OP_FMT_RI) {
LOG_DIS("sri r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5);
} else {
LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
/* The real CPU (w/o hardware shifter) only supports right shift by exactly
* one bit */
if (dc->format == OP_FMT_RI) {
if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
qemu_log_mask(LOG_GUEST_ERROR,
"hardware shifter is not available\n");
t_gen_illegal_insn(dc);
return;
}
tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
} else {
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
TCGv t0 = tcg_temp_local_new();
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
if (!(dc->features & LM32_FEATURE_SHIFT)) {
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
t_gen_illegal_insn(dc);
tcg_gen_br(l2);
}
gen_set_label(l1);
tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
gen_set_label(l2);
tcg_temp_free(t0);
}
}