static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
int ret;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
&i2s->playback_dma_data.addr,
&i2s->playback_dma_data.req_sel);
i2s->playback_dma_data.wrap = 4;
i2s->playback_dma_data.width = 32;
tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
i2s->playback_fifo_cif);
} else {
ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
&i2s->capture_dma_data.addr,
&i2s->capture_dma_data.req_sel);
i2s->capture_dma_data.wrap = 4;
i2s->capture_dma_data.width = 32;
tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
i2s->capture_i2s_cif);
}
return ret;
}
static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
int ret;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
&i2s->playback_dma_data.addr,
&i2s->playback_dma_data.slave_id);
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->playback_dma_data.maxburst = 4;
tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
i2s->playback_fifo_cif);
} else {
ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
&i2s->capture_dma_data.addr,
&i2s->capture_dma_data.slave_id);
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->capture_dma_data.maxburst = 4;
tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
i2s->capture_i2s_cif);
}
return ret;
}
static int tegra_max98095_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
if ((substream->stream != SNDRV_PCM_STREAM_PLAYBACK) ||
!(i2s->is_dam_used))
return 0;
/*dam configuration*/
if (!i2s->dam_ch_refcount)
i2s->dam_ifc = tegra30_dam_allocate_controller();
tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
i2s->dam_ch_refcount++;
tegra30_dam_enable_clock(i2s->dam_ifc);
tegra30_dam_set_gain(i2s->dam_ifc, TEGRA30_DAM_CHIN1, 0x1000);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
(i2s->dam_ifc*2), i2s->txcif);
/*
*make the dam tx to i2s rx connection if this is the only client
*using i2s for playback
*/
if (i2s->playback_ref_count == 1)
tegra30_ahub_set_rx_cif_source(
TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->dam_ifc);
/* enable the dam*/
tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN1);
return 0;
}
int tegra30_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
int ret = 0;
tegra30_spdif_enable_clocks(spdif);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = tegra30_ahub_allocate_tx_fifo(&spdif->txcif,
&spdif->playback_dma_data.addr,
&spdif->playback_dma_data.req_sel);
spdif->playback_dma_data.wrap = 4;
spdif->playback_dma_data.width = 32;
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_SPDIF_RX0,
spdif->txcif);
}
tegra30_spdif_disable_clocks(spdif);
return ret;
}
static int tegra_dmic_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct tegra_dmic *dmic = snd_soc_dai_get_drvdata(dai);
u32 dmic_cif_id;
int ret = 0;
mutex_lock(&dmic->mutex);
tegra30_ahub_enable_clocks();
ret = clk_enable(dmic->clk);
if (ret < 0)
dev_err(dmic->dev, "Can't enable DMIC clock\n");
/* Obtain Rx FIFOs and setup connections. */
ret = tegra30_ahub_allocate_rx_fifo(&dmic->rx_cif,
&dmic->capture_dma_data.addr,
&dmic->capture_dma_data.req_sel);
dmic->capture_dma_data.wrap = 4;
dmic->capture_dma_data.width = 32;
if (dai->id == TEGRA_DMIC_FRONT)
dmic_cif_id = TEGRA30_AHUB_TXCIF_DMIC0_TX0;
else if (dai->id == TEGRA_DMIC_BACK)
dmic_cif_id = TEGRA30_AHUB_TXCIF_DMIC1_TX0;
else
return -EINVAL;
tegra30_ahub_set_rx_cif_source(dmic->rx_cif,
dmic_cif_id);
mutex_unlock(&dmic->mutex);
return ret;
}
static int tegra_max98088_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
struct tegra_max98088 *machine = snd_soc_card_get_drvdata(rtd->card);
struct codec_config *codec_info;
struct codec_config *bb_info;
int codec_index;
if (!i2s->is_dam_used)
return 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/*dam configuration*/
if (!i2s->dam_ch_refcount)
i2s->dam_ifc = tegra30_dam_allocate_controller();
tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
i2s->dam_ch_refcount++;
tegra30_dam_enable_clock(i2s->dam_ifc);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
(i2s->dam_ifc*2), i2s->txcif);
/*
*make the dam tx to i2s rx connection if this is the only client
*using i2s for playback
*/
if (i2s->playback_ref_count == 1)
tegra30_ahub_set_rx_cif_source(
TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->dam_ifc);
/* enable the dam*/
tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN1);
} else {
i2s->is_call_mode_rec = machine->is_call_mode;
if (!i2s->is_call_mode_rec)
return 0;
if (machine->is_device_bt)
codec_index = BT_SCO;
else
codec_index = HIFI_CODEC;
codec_info = &machine->codec_info[codec_index];
bb_info = &machine->codec_info[BASEBAND];
/* allocate a dam for voice call recording */
i2s->call_record_dam_ifc = tegra30_dam_allocate_controller();
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
TEGRA30_DAM_CHIN0_SRC);
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable_clock(i2s->call_record_dam_ifc);
/* configure the dam */
tegra_max98088_set_dam_cif(i2s->call_record_dam_ifc,
codec_info->rate, codec_info->channels,
codec_info->bitsize, 1, bb_info->rate,
bb_info->channels, bb_info->bitsize);
/* setup the connections for voice call record */
tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
(i2s->call_record_dam_ifc*2),
TEGRA30_AHUB_TXCIF_I2S0_TX0 + bb_info->i2s_id);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
(i2s->call_record_dam_ifc*2),
TEGRA30_AHUB_TXCIF_I2S0_TX0 + codec_info->i2s_id);
tegra30_ahub_set_rx_cif_source(i2s->rxcif,
TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->call_record_dam_ifc);
/* enable the dam*/
tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN0_SRC);
}
return 0;
}
static int tegra30_i2s_platform_probe(struct platform_device *pdev)
{
struct tegra30_i2s *i2s;
const struct of_device_id *match;
u32 cif_ids[2];
struct resource *mem, *memregion;
void __iomem *regs;
int ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
if (!i2s) {
dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, i2s);
match = of_match_device(tegra30_i2s_of_match, &pdev->dev);
if (!match) {
dev_err(&pdev->dev, "Error: No device match found\n");
ret = -ENODEV;
goto err;
}
i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
i2s->dai = tegra30_i2s_dai_template;
i2s->dai.name = dev_name(&pdev->dev);
ret = of_property_read_u32_array(pdev->dev.of_node,
"nvidia,ahub-cif-ids", cif_ids,
ARRAY_SIZE(cif_ids));
if (ret < 0)
goto err;
i2s->playback_i2s_cif = cif_ids[0];
i2s->capture_i2s_cif = cif_ids[1];
i2s->clk_i2s = clk_get(&pdev->dev, NULL);
if (IS_ERR(i2s->clk_i2s)) {
dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
ret = PTR_ERR(i2s->clk_i2s);
goto err;
}
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem) {
dev_err(&pdev->dev, "No memory resource\n");
ret = -ENODEV;
goto err_clk_put;
}
memregion = devm_request_mem_region(&pdev->dev, mem->start,
resource_size(mem), DRV_NAME);
if (!memregion) {
dev_err(&pdev->dev, "Memory region already claimed\n");
ret = -EBUSY;
goto err_clk_put;
}
regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
if (!regs) {
dev_err(&pdev->dev, "ioremap failed\n");
ret = -ENOMEM;
goto err_clk_put;
}
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra30_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
ret = PTR_ERR(i2s->regmap);
goto err_clk_put;
}
regcache_cache_only(i2s->regmap, true);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = tegra30_i2s_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->playback_dma_data.maxburst = 4;
ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
i2s->playback_dma_chan,
sizeof(i2s->playback_dma_chan),
&i2s->playback_dma_data.addr);
if (ret) {
dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
goto err_suspend;
}
ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
i2s->playback_fifo_cif);
if (ret) {
dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
goto err_free_tx_fifo;
}
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->capture_dma_data.maxburst = 4;
ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
i2s->capture_dma_chan,
sizeof(i2s->capture_dma_chan),
&i2s->capture_dma_data.addr);
if (ret) {
dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
goto err_unroute_tx_fifo;
}
ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
i2s->capture_i2s_cif);
if (ret) {
dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
goto err_free_rx_fifo;
}
ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
&i2s->dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
ret = -ENOMEM;
goto err_unroute_rx_fifo;
}
ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
&i2s->dma_config, i2s->playback_dma_chan,
i2s->capture_dma_chan);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
goto err_unregister_component;
}
return 0;
err_unregister_component:
snd_soc_unregister_component(&pdev->dev);
err_unroute_rx_fifo:
tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
err_free_rx_fifo:
tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
err_unroute_tx_fifo:
tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
err_free_tx_fifo:
tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
tegra30_i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
err_clk_put:
clk_put(i2s->clk_i2s);
err:
return ret;
}
static int tegra_aic326x_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
struct tegra_aic326x *machine = snd_soc_card_get_drvdata(rtd->card);
struct codec_config *codec_info;
struct codec_config *bb_info;
struct codec_config *hifi_info;
int codec_index;
if (!i2s->is_dam_used)
return 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/*
*make apbif tx to i2s rx connection if this is the only client
*using i2s for playback
*/
if (i2s->playback_ref_count == 1) {
tegra30_ahub_set_rx_cif_source(
TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
i2s->txcif);
tegra30_ahub_enable_clocks();
}
} else {
i2s->is_call_mode_rec = machine->is_call_mode;
if (!i2s->is_call_mode_rec)
return 0;
if (machine->is_device_bt)
codec_index = BT_SCO;
else
codec_index = VOICE_CODEC;
codec_info = &machine->codec_info[codec_index];
bb_info = &machine->codec_info[BASEBAND];
hifi_info = &machine->codec_info[HIFI_CODEC];
/* allocate a dams for voice call recording */
i2s->call_record_dam_ifc = tegra30_dam_allocate_controller();
if (i2s->call_record_dam_ifc < 0)
return i2s->call_record_dam_ifc;
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
TEGRA30_DAM_CHIN0_SRC);
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable_clock(i2s->call_record_dam_ifc);
i2s->call_record_dam_ifc2 = tegra30_dam_allocate_controller();
if (i2s->call_record_dam_ifc2 < 0)
return i2s->call_record_dam_ifc2;
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc2,
TEGRA30_DAM_CHIN0_SRC);
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc2,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable_clock(i2s->call_record_dam_ifc2);
/* configure the dams */
/* DAM0 SRC bb rate to hifi rate */
tegra_aic326x_set_dam_cif(i2s->call_record_dam_ifc,
codec_info->rate, codec_info->channels,
codec_info->bitsize, 1, hifi_info->rate,
hifi_info->channels, hifi_info->bitsize);
/* DAM1 UL + DL Mix */
tegra_aic326x_set_dam_cif(i2s->call_record_dam_ifc2,
codec_info->rate, codec_info->channels,
codec_info->bitsize, 1, bb_info->rate,
bb_info->channels, bb_info->bitsize);
/* setup the connections for voice call record */
tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
(i2s->call_record_dam_ifc2*2),
TEGRA30_AHUB_TXCIF_I2S0_TX0 + bb_info->i2s_id);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
(i2s->call_record_dam_ifc2*2),
TEGRA30_AHUB_TXCIF_I2S0_TX0 + codec_info->i2s_id);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
(i2s->call_record_dam_ifc*2),
TEGRA30_AHUB_TXCIF_DAM0_TX0 +
i2s->call_record_dam_ifc2);
tegra30_ahub_set_rx_cif_source(i2s->rxcif,
TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->call_record_dam_ifc);
#ifndef CONFIG_ARCH_TEGRA_3x_SOC
/* Configure DAM0 for SRC */
if (bb_info->rate != hifi_info->rate) {
tegra30_dam_write_coeff_ram(i2s->call_record_dam_ifc,
bb_info->rate, hifi_info->rate);
tegra30_dam_set_farrow_param(i2s->call_record_dam_ifc,
bb_info->rate, hifi_info->rate);
tegra30_dam_set_biquad_fixed_coef(
i2s->call_record_dam_ifc);
tegra30_dam_enable_coeff_ram(i2s->call_record_dam_ifc);
tegra30_dam_set_filter_stages(i2s->call_record_dam_ifc,
bb_info->rate,
hifi_info->rate);
}
#endif
/* enable the dam */
tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN0_SRC);
tegra30_dam_enable(i2s->call_record_dam_ifc2,
TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable(i2s->call_record_dam_ifc2,
TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN0_SRC);
}
return 0;
}
