static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params)
{
struct clk *clk;
struct clk **dt_clk;
int i;
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
if (dt_clk) {
/* PLLP */
clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
pmc_base, 0, pll_params, NULL);
clk_register_clkdev(clk, "pll_p", NULL);
*dt_clk = clk;
}
for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
struct pll_out_data *data;
data = pllp_out_clks + i;
dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
if (!dt_clk)
continue;
clk = tegra_clk_register_divider(data->div_name, "pll_p",
clk_base + data->offset, 0, data->div_flags,
data->div_shift, 8, 1, data->lock);
clk = tegra_clk_register_pll_out(data->pll_out_name,
data->div_name, clk_base + data->offset,
data->rst_shift + 1, data->rst_shift,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
data->lock);
*dt_clk = clk;
}
}
static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params)
{
struct clk *clk;
struct clk **dt_clk;
int i;
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
if (dt_clk) {
/* PLLP */
clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
pmc_base, 0, pll_params, NULL);
clk_register_clkdev(clk, "pll_p", NULL);
*dt_clk = clk;
}
for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
struct pll_out_data *data;
data = pllp_out_clks + i;
dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
if (!dt_clk)
continue;
clk = tegra_clk_register_divider(data->div_name, "pll_p",
clk_base + data->offset, 0, data->div_flags,
data->div_shift, 8, 1, data->lock);
clk = tegra_clk_register_pll_out(data->pll_out_name,
data->div_name, clk_base + data->offset,
data->rst_shift + 1, data->rst_shift,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
data->lock);
*dt_clk = clk;
}
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
tegra_clks);
if (dt_clk) {
/*
* Tegra210 has control on enabling/disabling PLLP branches to
* CPU, register a gate clock "pll_p_out_cpu" for this gating
* function and parent "pll_p_out4" to it, so when we are
* re-parenting CPU off from "pll_p_out4" the PLLP branching to
* CPU can be disabled automatically.
*/
clk = tegra_clk_register_divider("pll_p_out4_div",
"pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
8, 1, &PLLP_OUTB_lock);
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
if (dt_clk) {
clk = tegra_clk_register_pll_out("pll_p_out4",
"pll_p_out4_div", clk_base + PLLP_OUTB,
17, 16, CLK_IGNORE_UNUSED |
CLK_SET_RATE_PARENT, 0,
&PLLP_OUTB_lock);
*dt_clk = clk;
}
}
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
if (dt_clk) {
/* PLLP_OUT_HSIO */
clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
clk_base + PLLP_MISC1, 29, 0, NULL);
*dt_clk = clk;
}
dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
if (dt_clk) {
/* PLLP_OUT_XUSB */
clk = clk_register_gate(NULL, "pll_p_out_xusb",
"pll_p_out_hsio", CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
NULL);
clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
*dt_clk = clk;
}
}
