static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, int is_lvds) { const struct tegra_dc *dc = sor->dc; const struct tegra_dc_dp_data *dp = dc->out; const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg; const struct soc_nvidia_tegra124_config *config = dc->config; const int head_num = 0; // based on kernel dc driver u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num; u32 vtotal, htotal; u32 vsync_end, hsync_end; u32 vblank_end, hblank_end; u32 vblank_start, hblank_start; reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM : NV_SOR_STATE1_ASY_PROTOCOL_DP_A; reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE | NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER; reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE; reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE; reg_val |= (link_cfg->bits_per_pixel > 18) ? NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 : NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444; tegra_sor_writel(sor, NV_SOR_STATE1, reg_val); /* Skipping programming NV_HEAD_STATE0, assuming: interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */ vtotal = config->vsync_width + config->vback_porch + config->yres + config->vfront_porch; htotal = config->hsync_width + config->hback_porch + config->xres + config->hfront_porch; tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT | htotal << NV_HEAD_STATE1_HTOTAL_SHIFT); vsync_end = config->vsync_width - 1; hsync_end = config->hsync_width - 1; tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT | hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT); vblank_end = vsync_end + config->vback_porch; hblank_end = hsync_end + config->hback_porch; tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT | hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT); vblank_start = vblank_end + config->yres; hblank_start = hblank_end + config->xres; tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT | hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT); /* TODO: adding interlace mode support */ tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); tegra_sor_write_field(sor, NV_SOR_CSTM, NV_SOR_CSTM_ROTCLK_DEFAULT_MASK | NV_SOR_CSTM_LVDS_EN_ENABLE, 2 << NV_SOR_CSTM_ROTCLK_SHIFT | (is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE : NV_SOR_CSTM_LVDS_EN_DISABLE)); tegra_dc_sor_config_pwm(sor, 1024, 1024); }
static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, int is_lvds, const struct tegra_dp_link_config *link_cfg, const struct display_timing *timing) { const int head_num = 0; u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num; u32 vtotal, htotal; u32 vsync_end, hsync_end; u32 vblank_end, hblank_end; u32 vblank_start, hblank_start; reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM : STATE1_ASY_PROTOCOL_DP_A; reg_val |= STATE1_ASY_SUBOWNER_NONE | STATE1_ASY_CRCMODE_COMPLETE_RASTER; reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE; reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE; reg_val |= (link_cfg->bits_per_pixel > 18) ? STATE1_ASY_PIXELDEPTH_BPP_24_444 : STATE1_ASY_PIXELDEPTH_BPP_18_444; tegra_sor_writel(sor, STATE1, reg_val); /* * Skipping programming NV_HEAD_STATE0, assuming: * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */ vtotal = timing->vsync_len.typ + timing->vback_porch.typ + timing->vactive.typ + timing->vfront_porch.typ; htotal = timing->hsync_len.typ + timing->hback_porch.typ + timing->hactive.typ + timing->hfront_porch.typ; tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT | htotal << NV_HEAD_STATE1_HTOTAL_SHIFT); vsync_end = timing->vsync_len.typ - 1; hsync_end = timing->hsync_len.typ - 1; tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT | hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT); vblank_end = vsync_end + timing->vback_porch.typ; hblank_end = hsync_end + timing->hback_porch.typ; tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT | hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT); vblank_start = vblank_end + timing->vactive.typ; hblank_start = hblank_end + timing->hactive.typ; tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT | hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT); /* TODO: adding interlace mode support */ tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); tegra_sor_write_field(sor, CSTM, CSTM_ROTCLK_DEFAULT_MASK | CSTM_LVDS_EN_ENABLE, 2 << CSTM_ROTCLK_SHIFT | is_lvds ? CSTM_LVDS_EN_ENABLE : CSTM_LVDS_EN_DISABLE); tegra_dc_sor_config_pwm(sor, 1024, 1024); }