C++ (Cpp) tegra_dc_sor_enable_lane_sequencer示例

示例#1

文件： sor.c 项目： AdriDlu/coreboot

static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
	u32 lane_count, int pu)
{
	u32 reg_val;

	reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));

	if (pu) {
		switch (lane_count) {
		case 4:
			reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
				NV_SOR_DP_PADCTL_PD_TXD_2_NO);
			/* fall through */
		case 2:
			reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
		case 1:
			reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
			break;
		default:
			printk(BIOS_ERR,
				"dp: invalid lane number %d\n", lane_count);
			return -1;
		}

		tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
		tegra_dc_sor_set_lane_count(sor, lane_count);
	}
	return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
}

示例#2

文件： sor.c 项目： Noltari/u-boot

static int tegra_dc_sor_power_dplanes(struct udevice *dev,
				      u32 lane_count, int pu)
{
	struct tegra_dc_sor_data *sor = dev_get_priv(dev);
	u32 reg_val;

	reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));

	if (pu) {
		switch (lane_count) {
		case 4:
			reg_val |= (DP_PADCTL_PD_TXD_3_NO |
				DP_PADCTL_PD_TXD_2_NO);
			/* fall through */
		case 2:
			reg_val |= DP_PADCTL_PD_TXD_1_NO;
		case 1:
			reg_val |= DP_PADCTL_PD_TXD_0_NO;
			break;
		default:
			debug("dp: invalid lane number %d\n", lane_count);
			return -1;
		}

		tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
		tegra_dc_sor_set_lane_count(dev, lane_count);
	}

	return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
}

示例#3

文件： sor.c 项目： AdriDlu/coreboot

void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor)
{
	u32 pad_ctrl = 0;
	int err = 0;

	switch (sor->link_cfg->lane_count) {
	case 4:
		pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
			NV_SOR_DP_PADCTL_PD_TXD_1_NO |
			NV_SOR_DP_PADCTL_PD_TXD_2_NO |
			NV_SOR_DP_PADCTL_PD_TXD_3_NO);
		break;
	case 2:
		pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
			NV_SOR_DP_PADCTL_PD_TXD_1_NO |
			NV_SOR_DP_PADCTL_PD_TXD_2_YES |
			NV_SOR_DP_PADCTL_PD_TXD_3_YES);
		break;
	case 1:
		pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO |
			NV_SOR_DP_PADCTL_PD_TXD_1_YES |
			NV_SOR_DP_PADCTL_PD_TXD_2_YES |
			NV_SOR_DP_PADCTL_PD_TXD_3_YES);
		break;
	default:
		printk(BIOS_ERR, "Invalid sor lane count: %u\n",
			sor->link_cfg->lane_count);
		return;
	}

	pad_ctrl |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN;
	tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), pad_ctrl);

	err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
	if (err) {
		printk(BIOS_ERR,
			"Wait for lane power down failed: %d\n", err);
		return;
	}
}

示例#4

文件： sor.c 项目： Noltari/u-boot

void tegra_dc_sor_power_down_unused_lanes(struct udevice *dev,
			const struct tegra_dp_link_config *link_cfg)
{
	struct tegra_dc_sor_data *sor = dev_get_priv(dev);
	u32 pad_ctrl = 0;
	int err = 0;

	switch (link_cfg->lane_count) {
	case 4:
		pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
			DP_PADCTL_PD_TXD_1_NO |
			DP_PADCTL_PD_TXD_2_NO |
			DP_PADCTL_PD_TXD_3_NO;
		break;
	case 2:
		pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
			DP_PADCTL_PD_TXD_1_NO |
			DP_PADCTL_PD_TXD_2_YES |
			DP_PADCTL_PD_TXD_3_YES;
		break;
	case 1:
		pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
			DP_PADCTL_PD_TXD_1_YES |
			DP_PADCTL_PD_TXD_2_YES |
			DP_PADCTL_PD_TXD_3_YES;
		break;
	default:
		printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
		return;
	}

	pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
	tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);

	err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
	if (err) {
		debug("Wait for lane power down failed: %d\n", err);
		return;
	}
}