int tegra_emc_timers_init(struct dentry *parent) { #ifdef CONFIG_DEBUG_FS struct dentry *dram_therm_debugfs; struct dentry *training_debugfs; /* * If caller doesn't want us to make a debugfs dir it can pass NULL. * This should never be a top level debugfs dir. For subsequent debugfs * errors return 0 - don't fail the entire EMC driver init if debugfs * has problems. We do a best effort here. */ if (!parent) return 0; emc_timers_debugfs = debugfs_create_dir("emc_timers", parent); if (!emc_timers_debugfs) return 0; dram_therm_debugfs = debugfs_create_dir("dram_therm", emc_timers_debugfs); if (!dram_therm_debugfs) return 0; debugfs_create_u32("debug", S_IRUGO | S_IWUSR, emc_timers_debugfs, &emc_timers_dbg); /* DRAM thermals. */ debugfs_create_u32("timer_period", S_IRUGO | S_IWUSR, dram_therm_debugfs, &timer_period_mr4); debugfs_create_u32("test_mode", S_IRUGO | S_IWUSR, dram_therm_debugfs, &test_mode); debugfs_create_u32("dram_temp_override", S_IRUGO | S_IWUSR, dram_therm_debugfs, &dram_temp_override); debugfs_create_file("force_poll", S_IRUGO | S_IWUSR, dram_therm_debugfs, NULL, &mr4_force_poll_fops); if (tegra_emc_get_dram_type() == DRAM_TYPE_LPDDR4) { /* Training. */ training_debugfs = debugfs_create_dir("training", emc_timers_debugfs); if (!training_debugfs) return 0; debugfs_create_u32("timer_period", S_IRUGO | S_IWUSR, training_debugfs, &timer_period_training); } #endif return 0; }
int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail) { if (tegra_emc_get_dram_type() != DRAM_TYPE_DDR3) return 0; if (((&tegra3_dvfs_rail_vdd_core == rail) && (rail->nominal_millivolts > TEGRA_EMC_BRIDGE_MVOLTS_MIN)) || ((&tegra3_dvfs_rail_vdd_cpu == rail) && (tegra3_get_core_floor_mv(rail->nominal_millivolts) > TEGRA_EMC_BRIDGE_MVOLTS_MIN))) { struct clk *bridge = tegra_get_clock_by_name("bridge.emc"); BUG_ON(!bridge); clk_disable(bridge); pr_info("%s: %s: disabled bridge.emc\n", __func__, rail->reg_id); } return 0; }