static int tegra_idle_enter_lp2(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
ktime_t enter, exit;
s64 us;
if (!lp2_in_idle || lp2_disabled_by_suspend ||
!tegra_lp2_is_allowed(dev, state))
return tegra_idle_enter_lp3(dev, state);
local_irq_disable();
enter = ktime_get();
tegra_cpu_idle_stats_lp2_ready(dev->cpu);
tegra_idle_lp2(dev, state);
exit = ktime_sub(ktime_get(), enter);
us = ktime_to_us(exit);
local_irq_enable();
/* cpu clockevents may have been reset by powerdown */
hrtimer_peek_ahead_timers();
smp_rmb();
state->exit_latency = tegra_lp2_exit_latency;
state->target_residency = tegra_lp2_exit_latency +
tegra_lp2_power_off_time;
if (state->target_residency < tegra_lp2_min_residency)
state->target_residency = tegra_lp2_min_residency;
tegra_cpu_idle_stats_lp2_time(dev->cpu, us);
return (int)us;
}
static int tegra_idle_enter_lp2(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
ktime_t enter, exit;
s64 us;
if (!lp2_in_idle || lp2_disabled_by_suspend ||
!tegra_lp2_is_allowed(dev, state)) {
dev->last_state = &dev->states[0];
return tegra_idle_enter_lp3(dev, state);
}
trace_printk("LP2 entry at %lu us\n",
(unsigned long)readl(IO_ADDRESS(TEGRA_TMR1_BASE)
+ TIMERUS_CNTR_1US));
local_irq_disable();
enter = ktime_get();
tegra_cpu_idle_stats_lp2_ready(dev->cpu);
tegra_idle_lp2(dev, state);
trace_printk("LP2 exit at %lu us\n",
(unsigned long)readl(IO_ADDRESS(TEGRA_TMR1_BASE)
+ TIMERUS_CNTR_1US));
exit = ktime_sub(ktime_get(), enter);
us = ktime_to_us(exit);
local_irq_enable();
smp_rmb();
/* Update LP2 latency provided no fall back to LP3 */
if (state == dev->last_state) {
tegra_lp2_set_global_latency(state);
tegra_lp2_update_target_residency(state);
}
tegra_cpu_idle_stats_lp2_time(dev->cpu, us);
return (int)us;
}
static int tegra_idle_enter_lp2(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
ktime_t enter, exit;
s64 us;
if (!lp2_in_idle || lp2_disabled_by_suspend ||
!tegra_lp2_is_allowed(dev, state)) {
dev->last_state = &dev->states[0];
return tegra_idle_enter_lp3(dev, state);
}
local_irq_disable();
enter = ktime_get();
tegra_cpu_idle_stats_lp2_ready(dev->cpu);
tegra_idle_lp2(dev, state);
exit = ktime_sub(ktime_get(), enter);
us = ktime_to_us(exit);
local_irq_enable();
/* cpu clockevents may have been reset by powerdown */
hrtimer_peek_ahead_timers();
smp_rmb();
/* Update LP2 latency provided no fall back to LP3 */
if (state == dev->last_state) {
tegra_lp2_set_global_latency(state);
tegra_lp2_update_target_residency(state);
}
tegra_cpu_idle_stats_lp2_time(dev->cpu, us);
return (int)us;
}