void __init tegra_pmc_init(void)
{
bool invert_interrupt = true;
u32 val;
#ifdef CONFIG_OF
if (of_have_populated_dt()) {
struct device_node *np;
invert_interrupt = false;
np = of_find_matching_node(NULL, matches);
if (np) {
if (of_find_property(np, "nvidia,invert-interrupt",
NULL))
invert_interrupt = true;
}
}
#endif
val = tegra_pmc_readl(PMC_CTRL);
if (invert_interrupt)
val |= PMC_CTRL_INTR_LOW;
else
val &= ~PMC_CTRL_INTR_LOW;
tegra_pmc_writel(val, PMC_CTRL);
}
void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
{
u32 val;
val = tegra_pmc_readl(0);
val |= 0x10;
tegra_pmc_writel(val, 0);
}
void tegra_pmc_suspend_init(void)
{
u32 reg;
/* Always enable CPU power request */
reg = tegra_pmc_readl(PMC_CTRL);
reg |= TEGRA_POWER_CPU_PWRREQ_OE;
tegra_pmc_writel(reg, PMC_CTRL);
}
void __init tegra_pmc_init(void)
{
u32 val;
tegra_pmc_parse_dt();
val = tegra_pmc_readl(PMC_CTRL);
if (tegra_pmc_invert_interrupt)
val |= PMC_CTRL_INTR_LOW;
else
val &= ~PMC_CTRL_INTR_LOW;
tegra_pmc_writel(val, PMC_CTRL);
}
void tegra_pmc_suspend_init(void)
{
u32 reg;
/* Always enable CPU power request */
reg = tegra_pmc_readl(PMC_CTRL);
reg |= TEGRA_POWER_CPU_PWRREQ_OE;
tegra_pmc_writel(reg, PMC_CTRL);
reg = tegra_pmc_readl(PMC_CTRL);
if (!pmc_pm_data.sysclkreq_high)
reg |= TEGRA_POWER_SYSCLK_POLARITY;
else
reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
/* configure the output polarity while the request is tristated */
tegra_pmc_writel(reg, PMC_CTRL);
/* now enable the request */
reg |= TEGRA_POWER_SYSCLK_OE;
tegra_pmc_writel(reg, PMC_CTRL);
}
void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
{
u32 val;
val = tegra_pmc_readl(PMC_SCRATCH0);
val &= ~PMC_SCRATCH0_MODE_MASK;
if (cmd) {
if (strcmp(cmd, "recovery") == 0)
val |= PMC_SCRATCH0_MODE_RECOVERY;
if (strcmp(cmd, "bootloader") == 0)
val |= PMC_SCRATCH0_MODE_BOOTLOADER;
if (strcmp(cmd, "forced-recovery") == 0)
val |= PMC_SCRATCH0_MODE_RCM;
}
tegra_pmc_writel(val, PMC_SCRATCH0);
val = tegra_pmc_readl(0);
val |= 0x10;
tegra_pmc_writel(val, 0);
}
void __init tegra_pmc_init_irq(void)
{
struct device_node *np;
u32 val;
np = of_find_matching_node(NULL, matches);
BUG_ON(!np);
tegra_pmc_base = of_iomap(np, 0);
tegra_pmc_invert_interrupt = of_property_read_bool(np,
"nvidia,invert-interrupt");
val = tegra_pmc_readl(PMC_CTRL);
if (tegra_pmc_invert_interrupt)
val |= PMC_CTRL_INTR_LOW;
else
val &= ~PMC_CTRL_INTR_LOW;
tegra_pmc_writel(val, PMC_CTRL);
}
void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
{
u32 reg;
unsigned long rate = 0;
reg = tegra_pmc_readl(PMC_CTRL);
reg |= TEGRA_POWER_CPU_PWRREQ_OE;
reg &= ~TEGRA_POWER_EFFECT_LP0;
switch (mode) {
case TEGRA_SUSPEND_LP2:
rate = clk_get_rate(tegra_pclk);
break;
default:
break;
}
set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
rate);
tegra_pmc_writel(reg, PMC_CTRL);
}
void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
{
u32 reg, csr_reg;
unsigned long rate = 0;
reg = tegra_pmc_readl(PMC_CTRL);
reg |= TEGRA_POWER_CPU_PWRREQ_OE;
reg &= ~TEGRA_POWER_EFFECT_LP0;
switch (tegra_chip_id) {
case TEGRA20:
case TEGRA30:
break;
default:
/* Turn off CRAIL */
csr_reg = flowctrl_read_cpu_csr(0);
csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
flowctrl_write_cpu_csr(0, csr_reg);
break;
}
switch (mode) {
case TEGRA_SUSPEND_LP1:
rate = 32768;
break;
case TEGRA_SUSPEND_LP2:
rate = clk_get_rate(tegra_pclk);
break;
default:
break;
}
set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
rate);
tegra_pmc_writel(reg, PMC_CTRL);
}
