void tegra_dc_sor_set_lane_parm(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), link_cfg->drive_current); tegra_sor_writel(sor, PR(sor->portnum), link_cfg->preemphasis); tegra_sor_writel(sor, POSTCURSOR(sor->portnum), link_cfg->postcursor); tegra_sor_writel(sor, LVDS, 0); tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count); tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), DP_PADCTL_TX_PU_ENABLE | DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, DP_PADCTL_TX_PU_ENABLE | 2 << DP_PADCTL_TX_PU_VALUE_SHIFT); /* Precharge */ tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); udelay(20); tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); }
int tegra_dc_sor_set_voltage_swing(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 drive_current = 0; u32 pre_emphasis = 0; /* Set to a known-good pre-calibrated setting */ switch (link_cfg->link_bw) { case SOR_LINK_SPEED_G1_62: case SOR_LINK_SPEED_G2_7: drive_current = 0x13131313; pre_emphasis = 0; break; case SOR_LINK_SPEED_G5_4: debug("T124 does not support 5.4G link clock.\n"); default: debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw); return -ENOLINK; } tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current); tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis); return 0; }
void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor) { u32 reg_val; struct display_controller *disp_ctrl = (void *)sor->dc->base; tegra_dc_sor_enable_dc(sor); tegra_dc_sor_config_panel(sor, 0); WRITEL(0x9f00, &disp_ctrl->cmd.state_ctrl); WRITEL(0x9f, &disp_ctrl->cmd.state_ctrl); WRITEL(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, &disp_ctrl->cmd.disp_pow_ctrl); reg_val = tegra_sor_readl(sor, NV_SOR_TEST); if (reg_val & NV_SOR_TEST_ATTACHED_TRUE) return; tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_NO); /* * Enable display2sor clock at least 2 cycles before DC start, * to clear sor internal valid signal. */ WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); WRITEL(0, &disp_ctrl->disp.disp_win_opt); WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); /* Attach head */ tegra_dc_sor_update(sor); tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_YES); tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, NV_SOR_SUPER_STATE1_ATTACHED_YES | NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE | NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL); tegra_dc_sor_super_update(sor); /* Enable dc */ reg_val = READL(&disp_ctrl->cmd.state_access); WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); WRITEL(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST, NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS * 1000)) printk(BIOS_ERR, "dc timeout waiting for OPMOD = AWAKE\n"); else printk(BIOS_INFO, "%s: sor is attached\n", __func__); #if DEBUG_SOR dump_sor_reg(sor); #endif }
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg) { tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), link_cfg->drive_current); tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), link_cfg->preemphasis); tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum), link_cfg->postcursor); tegra_sor_writel(sor, NV_SOR_LVDS, 0); tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), NV_SOR_DP_PADCTL_TX_PU_ENABLE | NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, NV_SOR_DP_PADCTL_TX_PU_ENABLE | 2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT); /* Precharge */ tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), 0xf0, 0xf0); udelay(20); tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), 0xf0, 0x0); }
void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, u8 training_pattern, const struct tegra_dc_dp_link_config *cfg) { u32 reg_val; reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum)); if (ena) reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES; else reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO; reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK; reg_val |= (cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT); if (cfg->enhanced_framing) reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE; tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val); switch (training_pattern) { case trainingPattern_1: tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141); break; case trainingPattern_2: case trainingPattern_3: reg_val = (cfg->link_bw == NV_SOR_LINK_SPEED_G5_4) ? 0x43434343 : 0x42424242; tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val); break; default: tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050); break; } }
int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); int dc_reg_ctx[DC_REG_SAVE_SPACE]; struct dc_ctlr *disp_ctrl; unsigned long dc_int_mask; int ret; debug("%s\n", __func__); /* Use the first display controller */ disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev); /* Sleep mode */ tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | SUPER_STATE1_ASY_ORMODE_SAFE | SUPER_STATE1_ATTACHED_YES); tegra_dc_sor_super_update(sor); tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx); if (tegra_dc_sor_poll_register(sor, TEST, TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, TEST_ACT_HEAD_OPMODE_SLEEP, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) { debug("dc timeout waiting for OPMOD = SLEEP\n"); ret = -ETIMEDOUT; goto err; } tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | SUPER_STATE1_ASY_ORMODE_SAFE | SUPER_STATE1_ATTACHED_NO); /* Mask DC interrupts during the 2 dummy frames required for detach */ dc_int_mask = readl(&disp_ctrl->cmd.int_mask); writel(0, &disp_ctrl->cmd.int_mask); /* Stop DC->SOR path */ tegra_dc_sor_enable_sor(disp_ctrl, false); ret = tegra_dc_sor_general_act(disp_ctrl); if (ret) goto err; /* Stop DC */ writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); ret = tegra_dc_sor_general_act(disp_ctrl); if (ret) goto err; tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx); writel(dc_int_mask, &disp_ctrl->cmd.int_mask); return 0; err: debug("%s: ret=%d\n", __func__, ret); return ret; }
void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor) { const struct tegra_dc_dp_link_config *link_cfg = sor->link_cfg; tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL, NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK, NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); udelay(25); tegra_sor_write_field(sor, NV_SOR_PLL3, NV_SOR_PLL3_PLLVDD_MODE_MASK, NV_SOR_PLL3_PLLVDD_MODE_V3_3); tegra_sor_writel(sor, NV_SOR_PLL0, 0xf << NV_SOR_PLL0_ICHPMP_SHFIT | 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT | NV_SOR_PLL0_PLLREG_LEVEL_V45 | NV_SOR_PLL0_RESISTORSEL_EXT | NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND); tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); tegra_sor_writel(sor, NV_SOR_PLL1, NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE); if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { printk(BIOS_ERR, "DP failed to lock PLL\n"); return; } tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE); tegra_dc_sor_power_up(sor, 0); /* re-enable SOR clock */ tegra_sor_enable_edp_clock(sor); // select pll_dp as clock source /* Power up lanes */ tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1); tegra_dc_sor_set_dp_mode(sor, link_cfg); }
void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor, u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu) { u32 d_cur; u32 p_emp; d_cur = tegra_sor_readl(sor, NV_SOR_DC(sor->portnum)); p_emp = tegra_sor_readl(sor, NV_SOR_PR(sor->portnum)); switch (lane) { case 0: p_emp &= ~NV_SOR_PR_LANE2_DP_LANE0_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE2_DP_LANE0_SHIFT); d_cur &= ~NV_SOR_DC_LANE2_DP_LANE0_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE2_DP_LANE0_SHIFT); break; case 1: p_emp &= ~NV_SOR_PR_LANE1_DP_LANE1_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE1_DP_LANE1_SHIFT); d_cur &= ~NV_SOR_DC_LANE1_DP_LANE1_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE1_DP_LANE1_SHIFT); break; case 2: p_emp &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE0_DP_LANE2_SHIFT); d_cur &= ~NV_SOR_DC_LANE0_DP_LANE2_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE0_DP_LANE2_SHIFT); break; case 3: p_emp &= ~NV_SOR_PR_LANE3_DP_LANE3_MASK; p_emp |= (pre_emphasis << NV_SOR_PR_LANE3_DP_LANE3_SHIFT); d_cur &= ~NV_SOR_DC_LANE3_DP_LANE3_MASK; d_cur |= (drive_current << NV_SOR_DC_LANE3_DP_LANE3_SHIFT); break; default: printk(BIOS_SPEW, "dp: sor lane count %d is invalid\n", lane); } tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum), NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, tx_pu << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT); tegra_sor_writel(sor, NV_SOR_DC(sor->portnum), d_cur); tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), p_emp); }
static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, u32 pwm_dutycycle) { tegra_sor_writel(sor, PWM_DIV, pwm_div); tegra_sor_writel(sor, PWM_CTL, (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) | PWM_CTL_SETTING_NEW_TRIGGER); if (tegra_dc_sor_poll_register(sor, PWM_CTL, PWM_CTL_SETTING_NEW_SHIFT, PWM_CTL_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS)) { debug("dp: timeout while waiting for SOR PWM setting\n"); } }
void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); reg_val &= ~DP_LINKCTL_LANECOUNT_MASK; switch (lane_count) { case 0: break; case 1: reg_val |= DP_LINKCTL_LANECOUNT_ONE; break; case 2: reg_val |= DP_LINKCTL_LANECOUNT_TWO; break; case 4: reg_val |= DP_LINKCTL_LANECOUNT_FOUR; break; default: /* 0 should be handled earlier. */ printf("dp: Invalid lane count %d\n", lane_count); return; } tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); }
static int tegra_dc_sor_power_dplanes(struct udevice *dev, u32 lane_count, int pu) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); if (pu) { switch (lane_count) { case 4: reg_val |= (DP_PADCTL_PD_TXD_3_NO | DP_PADCTL_PD_TXD_2_NO); /* fall through */ case 2: reg_val |= DP_PADCTL_PD_TXD_1_NO; case 1: reg_val |= DP_PADCTL_PD_TXD_0_NO; break; default: debug("dp: invalid lane number %d\n", lane_count); return -1; } tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); tegra_dc_sor_set_lane_count(dev, lane_count); } return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); }
static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, u32 lane_count, int pu) { u32 reg_val; reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum)); if (pu) { switch (lane_count) { case 4: reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); /* fall through */ case 2: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; case 1: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; default: printk(BIOS_ERR, "dp: invalid lane number %d\n", lane_count); return -1; } tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val); tegra_dc_sor_set_lane_count(sor, lane_count); } return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); }
int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd) { u32 reg_val; u32 orig_val; orig_val = tegra_sor_readl(sor, NV_SOR_PWR); reg_val = pu_pd ? NV_SOR_PWR_NORMAL_STATE_PU : NV_SOR_PWR_NORMAL_STATE_PD; /* normal state only */ if (reg_val == orig_val) return 0; /* No update needed */ reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER; tegra_sor_writel(sor, NV_SOR_PWR, reg_val); /* Poll to confirm it is done */ if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR, NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK, NV_SOR_PWR_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { printk(BIOS_ERR, "dc timeout waiting for SOR_PWR = NEW_DONE\n"); return -EFAULT; } return 0; }
static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor, const struct tegra_dc_dp_link_config *link_cfg) { u32 reg_val; tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg); reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum)); reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK; reg_val |= link_cfg->watermark; reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK; reg_val |= (link_cfg->active_count << NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT); reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK; reg_val |= (link_cfg->active_frac << NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT); if (link_cfg->activepolarity) reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; else reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE | NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE); tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val); /* program h/vblank sym */ tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym); tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, link_cfg->vblank_sym); }
void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count) { u32 reg_val; reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum)); reg_val &= ~NV_SOR_DP_LINKCTL_LANECOUNT_MASK; switch (lane_count) { case 0: break; case 1: reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_ONE; break; case 2: reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_TWO; break; case 4: reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_FOUR; break; default: /* 0 should be handled earlier. */ printk(BIOS_ERR, "dp: Invalid lane count %d\n", lane_count); return; } tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val); }
static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, int pu, int is_lvds) { u32 reg_val; /* SOR lane sequencer */ if (pu) { reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | LANE_SEQ_CTL_SEQUENCE_DOWN | LANE_SEQ_CTL_NEW_POWER_STATE_PU; } else { reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | LANE_SEQ_CTL_SEQUENCE_UP | LANE_SEQ_CTL_NEW_POWER_STATE_PD; } if (is_lvds) reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT; else reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT; tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val); if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL, LANE_SEQ_CTL_SETTING_MASK, LANE_SEQ_CTL_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS)) { debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n"); return -1; } return 0; }
static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, int pu, int is_lvds) { u32 reg_val; /* SOR lane sequencer */ if (pu) reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER | NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU; else reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER | NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP | NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD; if (is_lvds) reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT; else reg_val |= 1 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT; tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val); if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL, NV_SOR_LANE_SEQ_CTL_SETTING_MASK, NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS*1000)) { printk(BIOS_ERR, "dp: timeout while waiting for SOR lane sequencer " "to power down langes\n"); return -1; } return 0; }
int tegra_dc_sor_set_power_state(struct udevice *dev, int pu_pd) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; u32 orig_val; orig_val = tegra_sor_readl(sor, PWR); reg_val = pu_pd ? PWR_NORMAL_STATE_PU : PWR_NORMAL_STATE_PD; /* normal state only */ if (reg_val == orig_val) return 0; /* No update needed */ reg_val |= PWR_SETTING_NEW_TRIGGER; tegra_sor_writel(sor, PWR, reg_val); /* Poll to confirm it is done */ if (tegra_dc_sor_poll_register(sor, PWR, PWR_SETTING_NEW_DEFAULT_MASK, PWR_SETTING_NEW_DONE, 100, TEGRA_SOR_TIMEOUT_MS)) { debug("dc timeout waiting for SOR_PWR = NEW_DONE\n"); return -EFAULT; } return 0; }
static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, u32 reg, u32 mask, u32 val) { u32 reg_val = tegra_sor_readl(sor, reg); reg_val &= ~mask; reg_val |= val; tegra_sor_writel(sor, reg, reg_val); }
void tegra_dc_sor_set_panel_power(struct udevice *dev, int power_up) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); if (power_up) reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP; else reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP; tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); }
void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int) { u32 reg_val; reg_val = tegra_sor_readl(sor, NV_SOR_DP_SPARE(sor->portnum)); if (is_int) reg_val |= NV_SOR_DP_SPARE_PANEL_INTERNAL; else reg_val &= ~NV_SOR_DP_SPARE_PANEL_INTERNAL; reg_val |= NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK | NV_SOR_DP_SPARE_SEQ_ENABLE_YES; tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val); }
void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor) { u32 drive_current = 0; u32 pre_emphasis = 0; /* Set to a known-good pre-calibrated setting */ switch (sor->link_cfg->link_bw) { case SOR_LINK_SPEED_G1_62: case SOR_LINK_SPEED_G2_7: drive_current = 0x13131313; pre_emphasis = 0; break; case SOR_LINK_SPEED_G5_4: printk(BIOS_WARNING, "T124 does not support 5.4G link clock.\n"); default: printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n", sor->link_cfg->link_bw); return; } tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), drive_current); tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); }
void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 reg_val; reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); if (is_int) reg_val |= DP_SPARE_PANEL_INTERNAL; else reg_val &= ~DP_SPARE_PANEL_INTERNAL; reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK | DP_SPARE_SEQ_ENABLE_YES; tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val); }
void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, int power_up) { u32 reg_val; /* !!TODO: need to enable panel power through GPIO operations */ /* Check bug 790854 for HW progress */ reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum)); if (power_up) reg_val |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP; else reg_val &= ~NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP; tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val); }
void tegra_dc_sor_power_down_unused_lanes(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); u32 pad_ctrl = 0; int err = 0; switch (link_cfg->lane_count) { case 4: pad_ctrl = DP_PADCTL_PD_TXD_0_NO | DP_PADCTL_PD_TXD_1_NO | DP_PADCTL_PD_TXD_2_NO | DP_PADCTL_PD_TXD_3_NO; break; case 2: pad_ctrl = DP_PADCTL_PD_TXD_0_NO | DP_PADCTL_PD_TXD_1_NO | DP_PADCTL_PD_TXD_2_YES | DP_PADCTL_PD_TXD_3_YES; break; case 1: pad_ctrl = DP_PADCTL_PD_TXD_0_NO | DP_PADCTL_PD_TXD_1_YES | DP_PADCTL_PD_TXD_2_YES | DP_PADCTL_PD_TXD_3_YES; break; default: printf("Invalid sor lane count: %u\n", link_cfg->lane_count); return; } pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN; tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0); if (err) { debug("Wait for lane power down failed: %d\n", err); return; } }
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) { u32 pad_ctrl = 0; int err = 0; switch (sor->link_cfg->lane_count) { case 4: pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO | NV_SOR_DP_PADCTL_PD_TXD_1_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO | NV_SOR_DP_PADCTL_PD_TXD_3_NO); break; case 2: pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO | NV_SOR_DP_PADCTL_PD_TXD_1_NO | NV_SOR_DP_PADCTL_PD_TXD_2_YES | NV_SOR_DP_PADCTL_PD_TXD_3_YES); break; case 1: pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO | NV_SOR_DP_PADCTL_PD_TXD_1_YES | NV_SOR_DP_PADCTL_PD_TXD_2_YES | NV_SOR_DP_PADCTL_PD_TXD_3_YES); break; default: printk(BIOS_ERR, "Invalid sor lane count: %u\n", sor->link_cfg->lane_count); return; } pad_ctrl |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN; tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), pad_ctrl); err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0); if (err) { printk(BIOS_ERR, "Wait for lane power down failed: %d\n", err); return; } }
static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, int is_lvds) { const struct tegra_dc *dc = sor->dc; const struct tegra_dc_dp_data *dp = dc->out; const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg; const struct soc_nvidia_tegra124_config *config = dc->config; const int head_num = 0; // based on kernel dc driver u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num; u32 vtotal, htotal; u32 vsync_end, hsync_end; u32 vblank_end, hblank_end; u32 vblank_start, hblank_start; reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM : NV_SOR_STATE1_ASY_PROTOCOL_DP_A; reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE | NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER; reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE; reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE; reg_val |= (link_cfg->bits_per_pixel > 18) ? NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 : NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444; tegra_sor_writel(sor, NV_SOR_STATE1, reg_val); /* Skipping programming NV_HEAD_STATE0, assuming: interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */ vtotal = config->vsync_width + config->vback_porch + config->yres + config->vfront_porch; htotal = config->hsync_width + config->hback_porch + config->xres + config->hfront_porch; tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT | htotal << NV_HEAD_STATE1_HTOTAL_SHIFT); vsync_end = config->vsync_width - 1; hsync_end = config->hsync_width - 1; tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT | hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT); vblank_end = vsync_end + config->vback_porch; hblank_end = hsync_end + config->hback_porch; tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT | hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT); vblank_start = vblank_end + config->yres; hblank_start = hblank_end + config->xres; tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT | hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT); /* TODO: adding interlace mode support */ tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); tegra_sor_write_field(sor, NV_SOR_CSTM, NV_SOR_CSTM_ROTCLK_DEFAULT_MASK | NV_SOR_CSTM_LVDS_EN_ENABLE, 2 << NV_SOR_CSTM_ROTCLK_SHIFT | (is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE : NV_SOR_CSTM_LVDS_EN_DISABLE)); tegra_dc_sor_config_pwm(sor, 1024, 1024); }
static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor) { tegra_sor_writel(sor, NV_SOR_STATE0, 0); tegra_sor_writel(sor, NV_SOR_STATE0, 1); tegra_sor_writel(sor, NV_SOR_STATE0, 0); }
int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev, const struct tegra_dp_link_config *link_cfg, const struct display_timing *timing) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); struct dc_ctlr *disp_ctrl; u32 reg_val; /* Use the first display controller */ debug("%s\n", __func__); disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev); tegra_dc_sor_enable_dc(disp_ctrl); tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); writel(0x9f00, &disp_ctrl->cmd.state_ctrl); writel(0x9f, &disp_ctrl->cmd.state_ctrl); writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, &disp_ctrl->cmd.disp_pow_ctrl); reg_val = tegra_sor_readl(sor, TEST); if (reg_val & TEST_ATTACHED_TRUE) return -EEXIST; tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_NO); /* * Enable display2sor clock at least 2 cycles before DC start, * to clear sor internal valid signal. */ writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); writel(0, &disp_ctrl->disp.disp_win_opt); writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); /* Attach head */ tegra_dc_sor_update(sor); tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_YES); tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ATTACHED_YES | SUPER_STATE1_ASY_HEAD_OP_AWAKE | SUPER_STATE1_ASY_ORMODE_NORMAL); tegra_dc_sor_super_update(sor); /* Enable dc */ reg_val = readl(&disp_ctrl->cmd.state_access); writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); writel(reg_val, &disp_ctrl->cmd.state_access); if (tegra_dc_sor_poll_register(sor, TEST, TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, TEST_ACT_HEAD_OPMODE_AWAKE, 100, TEGRA_SOR_ATTACH_TIMEOUT_MS)) { printf("dc timeout waiting for OPMOD = AWAKE\n"); return -ETIMEDOUT; } else { debug("%s: sor is attached\n", __func__); } #if DEBUG_SOR dump_sor_reg(sor); #endif debug("%s: ret=%d\n", __func__, 0); return 0; }
int tegra_dc_sor_enable_dp(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); int ret; tegra_sor_write_field(sor, CLK_CNTRL, CLK_CNTRL_DP_CLK_SEL_MASK, CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); tegra_sor_write_field(sor, PLL2, PLL2_AUX6_BANDGAP_POWERDOWN_MASK, PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); udelay(25); tegra_sor_write_field(sor, PLL3, PLL3_PLLVDD_MODE_MASK, PLL3_PLLVDD_MODE_V3_3); tegra_sor_writel(sor, PLL0, 0xf << PLL0_ICHPMP_SHFIT | 0x3 << PLL0_VCOCAP_SHIFT | PLL0_PLLREG_LEVEL_V45 | PLL0_RESISTORSEL_EXT | PLL0_PWR_ON | PLL0_VCOPD_RESCIND); tegra_sor_write_field(sor, PLL2, PLL2_AUX1_SEQ_MASK | PLL2_AUX9_LVDSEN_OVERRIDE | PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | PLL2_AUX9_LVDSEN_OVERRIDE | PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | PLL1_TMDS_TERM_ENABLE); if (tegra_dc_sor_poll_register(sor, PLL2, PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, 100, TEGRA_SOR_TIMEOUT_MS)) { printf("DP failed to lock PLL\n"); return -EIO; } tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | PLL2_AUX7_PORT_POWERDOWN_MASK, PLL2_AUX2_OVERRIDE_POWERDOWN | PLL2_AUX7_PORT_POWERDOWN_DISABLE); ret = tegra_dc_sor_power_up(dev, 0); if (ret) { debug("DP failed to power up\n"); return ret; } /* re-enable SOR clock */ clock_sor_enable_edp_clock(); /* Power up lanes */ tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1); tegra_dc_sor_set_dp_mode(dev, link_cfg); debug("%s ret\n", __func__); return 0; }