static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) { unsigned long fcr = tup->fcr_shadow; int ret; if (tup->cdata->allow_txfifo_reset_fifo_mode) { fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_write(tup, fcr, UART_FCR); } else { fcr &= ~UART_FCR_ENABLE_FIFO; tegra_uart_write(tup, fcr, UART_FCR); udelay(60); fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_write(tup, fcr, UART_FCR); fcr |= UART_FCR_ENABLE_FIFO; tegra_uart_write(tup, fcr, UART_FCR); if (tup->cdata->fifo_mode_enable_status) { ret = tegra_uart_is_fifo_mode_enabled(tup); if (ret < 0) dev_err(tup->uport.dev, "FIFO mode not enabled\n"); } } /* Dummy read to ensure the write is posted */ tegra_uart_read(tup, UART_SCR); /* Wait for the flush to propagate. */ tegra_uart_wait_sym_time(tup, 2); }
static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) { unsigned long fcr = tup->fcr_shadow; if (tup->cdata->allow_txfifo_reset_fifo_mode) { fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_write(tup, fcr, UART_FCR); } else { fcr &= ~UART_FCR_ENABLE_FIFO; tegra_uart_write(tup, fcr, UART_FCR); udelay(60); fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_write(tup, fcr, UART_FCR); fcr |= UART_FCR_ENABLE_FIFO; tegra_uart_write(tup, fcr, UART_FCR); } /* Dummy read to ensure the write is posted */ tegra_uart_read(tup, UART_SCR); /* * For all tegra devices (up to t210), there is a hardware issue that * requires software to wait for 32 UART clock periods for the flush * to propagate, otherwise data could be lost. */ tegra_uart_wait_cycle_time(tup, 32); }
static void tegra_uart_enable_ms(struct uart_port *u) { struct tegra_uart_port *tup = to_tegra_uport(u); if (tup->enable_modem_interrupt) { tup->ier_shadow |= UART_IER_MSI; tegra_uart_write(tup, tup->ier_shadow, UART_IER); } }
static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) { unsigned long rate; unsigned int divisor; unsigned long lcr; int ret; if (tup->current_baud == baud) return 0; if (tup->cdata->support_clk_src_div) { rate = baud * 16; ret = clk_set_rate(tup->uart_clk, rate); if (ret < 0) { dev_err(tup->uport.dev, "clk_set_rate() failed for rate %lu\n", rate); return ret; } divisor = 1; } else { rate = clk_get_rate(tup->uart_clk); divisor = DIV_ROUND_CLOSEST(rate, baud * 16); } lcr = tup->lcr_shadow; lcr |= UART_LCR_DLAB; tegra_uart_write(tup, lcr, UART_LCR); tegra_uart_write(tup, divisor & 0xFF, UART_TX); tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); lcr &= ~UART_LCR_DLAB; tegra_uart_write(tup, lcr, UART_LCR); /* Dummy read to ensure the write is posted */ tegra_uart_read(tup, UART_SCR); tup->current_baud = baud; /* wait two character intervals at new rate */ tegra_uart_wait_sym_time(tup, 2); return 0; }
static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, unsigned int bytes) { if (bytes > TEGRA_UART_MIN_DMA) bytes = TEGRA_UART_MIN_DMA; tup->tx_in_progress = TEGRA_UART_TX_PIO; tup->tx_bytes = bytes; tup->ier_shadow |= UART_IER_THRI; tegra_uart_write(tup, tup->ier_shadow, UART_IER); }
static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl) { struct tegra_uart_port *tup = to_tegra_uport(u); unsigned long lcr; lcr = tup->lcr_shadow; if (break_ctl) lcr |= UART_LCR_SBC; else lcr &= ~UART_LCR_SBC; tegra_uart_write(tup, lcr, UART_LCR); tup->lcr_shadow = lcr; }
static void set_dtr(struct tegra_uart_port *tup, bool active) { unsigned long mcr; mcr = tup->mcr_shadow; if (active) mcr |= UART_MCR_DTR; else mcr &= ~UART_MCR_DTR; if (mcr != tup->mcr_shadow) { tegra_uart_write(tup, mcr, UART_MCR); tup->mcr_shadow = mcr; } }
static void set_rts(struct tegra_uart_port *tup, bool active) { unsigned long mcr; mcr = tup->mcr_shadow; if (active) mcr |= TEGRA_UART_MCR_RTS_EN; else mcr &= ~TEGRA_UART_MCR_RTS_EN; if (mcr != tup->mcr_shadow) { tegra_uart_write(tup, mcr, UART_MCR); tup->mcr_shadow = mcr; } }
static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) { unsigned long fcr = tup->fcr_shadow; if (tup->cdata->allow_txfifo_reset_fifo_mode) { fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_write(tup, fcr, UART_FCR); } else { fcr &= ~UART_FCR_ENABLE_FIFO; tegra_uart_write(tup, fcr, UART_FCR); udelay(60); fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_write(tup, fcr, UART_FCR); fcr |= UART_FCR_ENABLE_FIFO; tegra_uart_write(tup, fcr, UART_FCR); } /* Dummy read to ensure the write is posted */ tegra_uart_read(tup, UART_SCR); /* Wait for the flush to propagate. */ tegra_uart_wait_sym_time(tup, 1); }
static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) { unsigned long flags; unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); unsigned long fifo_empty_time = tup->uport.fifosize * char_time; unsigned long wait_time; unsigned long lsr; unsigned long msr; unsigned long mcr; /* Disable interrupts */ tegra_uart_write(tup, 0, UART_IER); lsr = tegra_uart_read(tup, UART_LSR); if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { msr = tegra_uart_read(tup, UART_MSR); mcr = tegra_uart_read(tup, UART_MCR); if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) dev_err(tup->uport.dev, "Tx Fifo not empty, CTS disabled, waiting\n"); /* Wait for Tx fifo to be empty */ while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) { wait_time = min(fifo_empty_time, 100lu); udelay(wait_time); fifo_empty_time -= wait_time; if (!fifo_empty_time) { msr = tegra_uart_read(tup, UART_MSR); mcr = tegra_uart_read(tup, UART_MCR); if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) dev_err(tup->uport.dev, "Slave not ready\n"); break; } lsr = tegra_uart_read(tup, UART_LSR); } } spin_lock_irqsave(&tup->uport.lock, flags); /* Reset the Rx and Tx FIFOs */ tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); tup->current_baud = 0; spin_unlock_irqrestore(&tup->uport.lock, flags); clk_disable_unprepare(tup->uart_clk); }
static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) { struct circ_buf *xmit = &tup->uport.state->xmit; int i; for (i = 0; i < max_bytes; i++) { BUG_ON(uart_circ_empty(xmit)); if (tup->cdata->tx_fifo_full_status) { unsigned long lsr = tegra_uart_read(tup, UART_LSR); if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL)) break; } tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); tup->uport.icount.tx++; } }
static void tegra_uart_stop_rx(struct uart_port *u) { struct tegra_uart_port *tup = to_tegra_uport(u); struct tty_struct *tty; struct tty_port *port = &u->state->port; struct dma_tx_state state; unsigned long ier; int count; if (tup->rts_active) set_rts(tup, false); if (!tup->rx_in_progress) return; tty = tty_port_tty_get(&tup->uport.state->port); tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ ier = tup->ier_shadow; ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD); tup->ier_shadow = ier; tegra_uart_write(tup, ier, UART_IER); tup->rx_in_progress = 0; if (tup->rx_dma_chan && !tup->use_rx_pio) { dmaengine_terminate_all(tup->rx_dma_chan); dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); async_tx_ack(tup->rx_dma_desc); count = tup->rx_bytes_requested - state.residue; if (count) tegra_uart_copy_rx_to_tty(tup, port, count); tegra_uart_handle_rx_pio(tup, port); } else { tegra_uart_handle_rx_pio(tup, port); } if (tty) { tty_flip_buffer_push(port); tty_kref_put(tty); } return; }
static void tegra_uart_stop_rx(struct uart_port *u) { struct tegra_uart_port *tup = to_tegra_uport(u); struct dma_tx_state state; unsigned long ier; if (tup->rts_active) set_rts(tup, false); if (!tup->rx_in_progress) return; tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ ier = tup->ier_shadow; ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD); tup->ier_shadow = ier; tegra_uart_write(tup, ier, UART_IER); tup->rx_in_progress = 0; dmaengine_terminate_all(tup->rx_dma_chan); dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); tegra_uart_rx_buffer_push(tup, state.residue); }
static int tegra_uart_hw_init(struct tegra_uart_port *tup) { int ret; tup->fcr_shadow = 0; tup->mcr_shadow = 0; tup->lcr_shadow = 0; tup->ier_shadow = 0; tup->current_baud = 0; clk_prepare_enable(tup->uart_clk); /* Reset the UART controller to clear all previous status.*/ reset_control_assert(tup->rst); udelay(10); reset_control_deassert(tup->rst); tup->rx_in_progress = 0; tup->tx_in_progress = 0; /* * Set the trigger level * * For PIO mode: * * For receive, this will interrupt the CPU after that many number of * bytes are received, for the remaining bytes the receive timeout * interrupt is received. Rx high watermark is set to 4. * * For transmit, if the trasnmit interrupt is enabled, this will * interrupt the CPU when the number of entries in the FIFO reaches the * low watermark. Tx low watermark is set to 16 bytes. * * For DMA mode: * * Set the Tx trigger to 16. This should match the DMA burst size that * programmed in the DMA registers. */ tup->fcr_shadow = UART_FCR_ENABLE_FIFO; tup->fcr_shadow |= UART_FCR_R_TRIG_01; tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); /* Dummy read to ensure the write is posted */ tegra_uart_read(tup, UART_SCR); /* * For all tegra devices (up to t210), there is a hardware issue that * requires software to wait for 3 UART clock periods after enabling * the TX fifo, otherwise data could be lost. */ tegra_uart_wait_cycle_time(tup, 3); /* * Initialize the UART with default configuration * (115200, N, 8, 1) so that the receive DMA buffer may be * enqueued */ tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); tup->fcr_shadow |= UART_FCR_DMA_SELECT; tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); ret = tegra_uart_start_rx_dma(tup); if (ret < 0) { dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); return ret; } tup->rx_in_progress = 1; /* * Enable IE_RXS for the receive status interrupts like line errros. * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. * * If using DMA mode, enable EORD instead of receive interrupt which * will interrupt after the UART is done with the receive instead of * the interrupt when the FIFO "threshold" is reached. * * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when * the DATA is sitting in the FIFO and couldn't be transferred to the * DMA as the DMA size alignment(4 bytes) is not met. EORD will be * triggered when there is a pause of the incomming data stream for 4 * characters long. * * For pauses in the data which is not aligned to 4 bytes, we get * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first * then the EORD. */ tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; tegra_uart_write(tup, tup->ier_shadow, UART_IER); return 0; }
static irqreturn_t tegra_uart_isr(int irq, void *data) { struct tegra_uart_port *tup = data; struct uart_port *u = &tup->uport; unsigned long iir; unsigned long ier; bool is_rx_int = false; unsigned long flags; spin_lock_irqsave(&u->lock, flags); while (1) { iir = tegra_uart_read(tup, UART_IIR); if (iir & UART_IIR_NO_INT) { if (is_rx_int) { tegra_uart_handle_rx_dma(tup); if (tup->rx_in_progress) { ier = tup->ier_shadow; ier |= (UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD); tup->ier_shadow = ier; tegra_uart_write(tup, ier, UART_IER); } } spin_unlock_irqrestore(&u->lock, flags); return IRQ_HANDLED; } switch ((iir >> 1) & 0x7) { case 0: /* Modem signal change interrupt */ tegra_uart_handle_modem_signal_change(u); break; case 1: /* Transmit interrupt only triggered when using PIO */ tup->ier_shadow &= ~UART_IER_THRI; tegra_uart_write(tup, tup->ier_shadow, UART_IER); tegra_uart_handle_tx_pio(tup); break; case 4: /* End of data */ case 6: /* Rx timeout */ case 2: /* Receive */ if (!is_rx_int) { is_rx_int = true; /* Disable Rx interrupts */ ier = tup->ier_shadow; ier |= UART_IER_RDI; tegra_uart_write(tup, ier, UART_IER); ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD); tup->ier_shadow = ier; tegra_uart_write(tup, ier, UART_IER); } break; case 3: /* Receive error */ tegra_uart_decode_rx_error(tup, tegra_uart_read(tup, UART_LSR)); break; case 5: /* break nothing to handle */ case 7: /* break nothing to handle */ break; } } }
static void tegra_uart_set_termios(struct uart_port *u, struct ktermios *termios, struct ktermios *oldtermios) { struct tegra_uart_port *tup = to_tegra_uport(u); unsigned int baud; unsigned long flags; unsigned int lcr; int symb_bit = 1; struct clk *parent_clk = clk_get_parent(tup->uart_clk); unsigned long parent_clk_rate = clk_get_rate(parent_clk); int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; max_divider *= 16; spin_lock_irqsave(&u->lock, flags); /* Changing configuration, it is safe to stop any rx now */ if (tup->rts_active) set_rts(tup, false); /* Clear all interrupts as configuration is going to be change */ tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); tegra_uart_read(tup, UART_IER); tegra_uart_write(tup, 0, UART_IER); tegra_uart_read(tup, UART_IER); /* Parity */ lcr = tup->lcr_shadow; lcr &= ~UART_LCR_PARITY; /* CMSPAR isn't supported by this driver */ termios->c_cflag &= ~CMSPAR; if ((termios->c_cflag & PARENB) == PARENB) { symb_bit++; if (termios->c_cflag & PARODD) { lcr |= UART_LCR_PARITY; lcr &= ~UART_LCR_EPAR; lcr &= ~UART_LCR_SPAR; } else { lcr |= UART_LCR_PARITY; lcr |= UART_LCR_EPAR; lcr &= ~UART_LCR_SPAR; } } lcr &= ~UART_LCR_WLEN8; switch (termios->c_cflag & CSIZE) { case CS5: lcr |= UART_LCR_WLEN5; symb_bit += 5; break; case CS6: lcr |= UART_LCR_WLEN6; symb_bit += 6; break; case CS7: lcr |= UART_LCR_WLEN7; symb_bit += 7; break; default: lcr |= UART_LCR_WLEN8; symb_bit += 8; break; } /* Stop bits */ if (termios->c_cflag & CSTOPB) { lcr |= UART_LCR_STOP; symb_bit += 2; } else { lcr &= ~UART_LCR_STOP; symb_bit++; } tegra_uart_write(tup, lcr, UART_LCR); tup->lcr_shadow = lcr; tup->symb_bit = symb_bit; /* Baud rate. */ baud = uart_get_baud_rate(u, termios, oldtermios, parent_clk_rate/max_divider, parent_clk_rate/16); spin_unlock_irqrestore(&u->lock, flags); tegra_set_baudrate(tup, baud); if (tty_termios_baud_rate(termios)) tty_termios_encode_baud_rate(termios, baud, baud); spin_lock_irqsave(&u->lock, flags); /* Flow control */ if (termios->c_cflag & CRTSCTS) { tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); /* if top layer has asked to set rts active then do so here */ if (tup->rts_active) set_rts(tup, true); } else { tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); } /* update the port timeout based on new settings */ uart_update_timeout(u, termios->c_cflag, baud); /* Make sure all write has completed */ tegra_uart_read(tup, UART_IER); /* Reenable interrupt */ tegra_uart_write(tup, tup->ier_shadow, UART_IER); tegra_uart_read(tup, UART_IER); spin_unlock_irqrestore(&u->lock, flags); }