static int tegra_ehci_setup(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); int retval; #ifndef CONFIG_ARCH_TEGRA_2x_SOC u32 val; #endif /* EHCI registers start at offset 0x100 */ ehci->caps = hcd->regs + 0x100; ehci->regs = hcd->regs + 0x100 + HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); dbg_hcs_params(ehci, "reset"); dbg_hcc_params(ehci, "reset"); /* cache this readonly data; minimize chip reads */ ehci->hcs_params = readl(&ehci->caps->hcs_params); ehci->has_hostpc = tegra->has_hostpc; ehci->broken_hostpc_phcd = true; #ifndef CONFIG_ARCH_TEGRA_2x_SOC ehci->has_hostpc = 1; val = readl(hcd->regs + HOSTPC_REG_OFFSET); val &= ~HOSTPC1_DEVLC_STS; val &= ~HOSTPC1_DEVLC_NYT_ASUS; writel(val, hcd->regs + HOSTPC_REG_OFFSET); #endif hcd->has_tt = 1; retval = ehci_halt(ehci); if (retval) return retval; /* data structure init */ retval = ehci_init(hcd); if (retval) return retval; ehci->sbrn = 0x20; ehci->controller_remote_wakeup = false; ehci_reset(ehci); tegra_usb_phy_reset(tegra->phy); #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \ !defined(CONFIG_TEGRA_SILICON_PLATFORM) val = readl(hcd->regs + TEGRA_STREAM_DISABLE); val |= TEGRA_STREAM_DISABLE_OFFSET; writel(val , hcd->regs + TEGRA_STREAM_DISABLE); #endif ehci_port_power(ehci, 1); return retval; }
static int tegra_ehci_setup(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); int retval; #ifndef CONFIG_ARCH_TEGRA_2x_SOC u32 val; #endif /* EHCI registers start at offset 0x100 */ ehci->caps = hcd->regs + 0x100; ehci->has_hostpc = tegra->has_hostpc; ehci->broken_hostpc_phcd = true; #ifndef CONFIG_ARCH_TEGRA_2x_SOC ehci->has_hostpc = 1; val = readl(hcd->regs + HOSTPC_REG_OFFSET); val &= ~HOSTPC1_DEVLC_STS; val &= ~HOSTPC1_DEVLC_NYT_ASUS; writel(val, hcd->regs + HOSTPC_REG_OFFSET); #endif /* switch to host mode */ hcd->has_tt = 1; retval = ehci_setup(hcd); if (retval) return retval; ehci->controller_remote_wakeup = false; tegra_usb_phy_reset(tegra->phy); #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) if (tegra_platform_is_fpga()) { val = readl(hcd->regs + TEGRA_STREAM_DISABLE); val |= TEGRA_STREAM_DISABLE_OFFSET; writel(val , hcd->regs + TEGRA_STREAM_DISABLE); } #endif return 0; }
static int tegra_ehci_setup(struct usb_hcd *hcd) { struct ehci_hcd *ehci = hcd_to_ehci(hcd); struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); int retval; /* EHCI registers start at offset 0x100 */ ehci->caps = hcd->regs + 0x100; ehci->regs = hcd->regs + 0x100 + HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); dbg_hcs_params(ehci, "reset"); dbg_hcc_params(ehci, "reset"); /* cache this readonly data; minimize chip reads */ ehci->hcs_params = readl(&ehci->caps->hcs_params); ehci->has_hostpc = tegra_usb_phy_has_hostpc(tegra->phy) ? 1 : 0; ehci->broken_hostpc_phcd = true; hcd->has_tt = 1; retval = ehci_halt(ehci); if (retval) return retval; /* data structure init */ retval = ehci_init(hcd); if (retval) return retval; ehci->sbrn = 0x20; ehci->controller_remote_wakeup = false; ehci_reset(ehci); tegra_usb_phy_reset(tegra->phy); ehci_port_power(ehci, 1); return retval; }