extern int
sq_spi_master_slave_mode3_test(int autotest)
{
int ret = 0;
cpha=SQ_SPI_CPHA_1;
cpol=SQ_SPI_CPOL_1;
if(pure)
ret = test_item_ctrl(&sq_spi_master_sb_test_container, autotest);
else
ret = test_item_ctrl(&sq_spi_slave_type_test_container, autotest);
return ret;
}
extern int sq_spi_master0_test(int autotest)
{
int ret = 0;
{
extern struct test_item sq_spi_transfer_test_items[];
sq_spi_transfer_test_items[1].enable = SQ_SPI_EEPROM_0_TEST;
sq_spi_transfer_test_items[2].enable = SQ_SPI_MARVEL_WIFI_0_TEST;
sq_spi_transfer_test_items[3].enable = SQ_SPI_TSC2000_0_TEST;
sq_spi_transfer_test_items[4].enable = SQ_SPI_AR7646_0_TEST;
}
sq_spi_base = SQ_APB0_SPI0;
#ifdef CONFIG_SQ8000
sq_scu_dev_enable(SQ_DEVCON_SPI0);
sq_scu_hdma_req45_spi0();
#endif
sq_spi_master_init(sq_spi_base,SQ_INTC_SPI0);
ret = test_item_ctrl(&sq_spi_transfer_test_container, autotest);
#ifdef CONFIG_SQ8000
sq_scu_dev_disable(SQ_DEVCON_SPI0);
#endif
sq_spi_master_free();
return ret;
}
extern int
sq_spi_master_test(int autotest)
{
int ret = 0;
ret = test_item_ctrl(&sq_spi_master_test_container, autotest);
return ret;
}
extern int
RTCTesting(int autotest)
{
int result = 0;
#if defined(CONFIG_LDK5) || defined(CONFIG_PDK) || defined(CONFIG_PC7210)
u32 check;
check = ioread32(SOCLE_RTC_TIME);
RESET_RTC_CIRCUIT();
MSDELAY(1000);
if(ioread32(SOCLE_RTC_TIME) == check)
RESET_RTC_COUNTER();
if (RTC_IS_PWFAIL) {
printf("Warning: RTC Power Fail!!\n");
printf("\tPlease change your battery and then reset RTC again...\n");
}
if(!RTC_IS_GOOD){
printf("RTC is not Power Good\n");
}
#endif //CONFIG_LDK5
RTC_SET_DIVIDER(RTC_DIVIDER);
RTC_EN();
result = test_item_ctrl(&rtc_main_container, autotest);
RTC_DIS();
return result;
}
extern int
SPITesting(int autotest)
{
int ret = 0;
ret = test_item_ctrl(&sq_spi_test_container, autotest);
return ret;
}
extern int
sq_spi_master_msb_test(int autotest)
{
int ret = 0;
lsb=SQ_SPI_TX_MSB_FIRST;
ret = test_item_ctrl(&sq_spi_master_ch_test_container, autotest);
return ret;
}
extern int
socle_audio_codec_adc_test(int autotest)
{
int ret;
ret = test_item_ctrl(&socle_audio_adc_input_ch_test_container, autotest);
return ret;
}
extern int
socle_audio_adc_input_ch2_test(int autotest)
{
int ret = 0;
socle_adc_channel_contrl(2);
ret = test_item_ctrl(&socle_audio_adc_control_test_container, autotest);
return ret;
}
extern int
sq_spi_master_slave_protocol_test(int autotest)
{
int ret = 0;
pure=0;
ret = test_item_ctrl(&sq_spi_master_slave_mode_test_container, autotest);
return ret;
}
extern int
bch4_ecc_corrected(int autotest)
{
int ret = 0;
nand_info->ecc_mode = 0;
ret = test_item_ctrl(&nfc_ctrl_ecc_correct_test_container, autotest);
return ret;
}
int nfc_ctrl_fpga_test(int autotest)
{
int ret = 0;
ret = test_item_ctrl(&nfc_fpga_test_container, autotest);
return ret;
}
extern int
rtc_alarm_test(int autotest)
{
int result = 0;
result = test_item_ctrl(&rtc_alarm_test_container, autotest);
return result;
}
extern int
socle_audio_codec_ms6335_test(int autotest)
{
int ret;
ret = test_item_ctrl(&socle_audio_codec_adc_dac_test_container, autotest);
return ret;
}
extern int
sq_spi_master_slave_reg_test(int autotest)
{
int ret = 0;
pure=1;
regflag=1;
ret = test_item_ctrl(&sq_spi_master_slave_mode_test_container, autotest);
return ret;
}
extern int
instruction_test(int autotest)
{
int ret = 0;
page_number = 0;
ret = test_item_ctrl(&nfc_ctrl_data_transfer_dma_test_container, autotest);
return ret;
}
extern int
instruction_without_dma_test(int autotest)
{
int ret = 0;
nand_info->dma_on = 0;
socle_nfc_set_dma(nand_info);
ret = test_item_ctrl(&nfc_ctrl_event_container, autotest);
return ret;
}
extern int
dma_transfer_size_16bit(int autotest)
{
int ret = 0;
nand_info->dma_size= NF_DMA_SIZE_16;
ret = test_item_ctrl(&nfc_ctrl_transfer_dma_mode_test_container, autotest);
return ret;
}
extern int
sq_other_test(int autotest)
{
int ret=0;
ret = test_item_ctrl(&sq_tps62353_regs_container, autotest);
return ret;
}
extern int fllookup_test(int autotest)
{
int ret = 0;
nand_info->dma_on =0;
nand_info->ecc_on = 0;
socle_nfc_set_ecc(nand_info);
ret = test_item_ctrl(&nfc_ctrl_fllookup_test_container, autotest);
return ret;
}
extern int
dma_transfer_size_32bit(int autotest)
{
int ret = 0;
nand_info->dma_size= NF_DMA_SIZE_32;
ret = test_item_ctrl(&nfc_ctrl_transfer_dma_mode_test_container, autotest);
//ret = socle_nand_page_read_program_loopback_test();
return ret;
}
extern int
instruction_with_dma_test(int autotest)
{
int ret = 0;
nand_info->dma_on= 1;
socle_nfc_set_dma(nand_info);
ret = test_item_ctrl(&nfc_ctrl_dma_transfer_size_test_container, autotest);
return ret;
}
extern int
tps62353_test(int autotest)
{
int ret;
tps62353_client.addr = TPS62353_I2C_CLIENT_ADDR;
ret = tps62353_en_dcdc_set(&tps62353_client, 1); //device enable
if(ret == -1){
printf("tps62353 enable fails\n");
return -1;
}
ret = test_item_ctrl(&sq_tps62353_main_container, autotest);
return ret;
}
extern int
sq_voltage_test(int autotest)
{
int ret=0;
if(tps62353_type == 0){
tps62353_vsm_set = tps62353_vsm0_set;
tps62353_vsm_get = tps62353_vsm0_get;
}else{
tps62353_vsm_set = tps62353_vsm1_set;
tps62353_vsm_get = tps62353_vsm1_get;
}
ret = test_item_ctrl(&sq_tps62353_voltage_container, autotest);
return ret;
}
extern int
sq_spi_internal_hdma_test(int autotest)
{
int ret = 0;
sq_spi_tx_dma_ext_hdreq = 5;
sq_spi_rx_dma_ext_hdreq = 4;
sq_spi_tx_dma_ch_num = PANTHER7_HDMA_CH_1;
sq_spi_rx_dma_ch_num = PANTHER7_HDMA_CH_0;
sq_request_dma(sq_spi_tx_dma_ch_num, &sq_spi_tx_dma_notifier);
sq_request_dma(sq_spi_rx_dma_ch_num, &sq_spi_rx_dma_notifier);
ret = test_item_ctrl(&sq_spi_hdma_burst_type_test_container, autotest);
sq_disable_dma(sq_spi_tx_dma_ch_num);
sq_disable_dma(sq_spi_rx_dma_ch_num);
sq_free_dma(sq_spi_tx_dma_ch_num);
sq_free_dma(sq_spi_rx_dma_ch_num);
return ret;
}
extern int
ecc_correction_test(int autotest)
{
int ret = 0;
nand_info->dma_on = 0;
nand_info->ecc_on = 1;
socle_nfc_set_ecc(nand_info);
reference_page = socle_get_test_page_number();
target_page = reference_page+1;
page_number++;
socle_nand_initial_buf(BUFFER_WRITE);
if (socle_nfc_page_program_memory(nand_info, reference_page, nand_info->flash_info->page_size))
return -1;
ret = test_item_ctrl(&nfc_ctrl_ecc_correct_mode_test_container, autotest);
nand_info->ecc_on = 0;
socle_nfc_set_ecc(nand_info);
return ret;
}
int nfc_ctrl_test (int autotest)
{
int ret = 0;
int auto_boot_fail = 0;
if (nfc_mode == fpga_axi) {
nand_info->io_base = 0x30040000 + NF_SFR_ADDRESS_OFFSET;
nand_info->buf_addr = 0x30040000;
}else if (nfc_mode == fpga_ahb) {
nand_info->io_base = 0x20040000 + NF_SFR_ADDRESS_OFFSET;
nand_info->buf_addr = 0x20040000;
}else {
nand_info->io_base = NF_CONTROLLER_ADDRESS + NF_SFR_ADDRESS_OFFSET;
nand_info->buf_addr = NF_CONTROLLER_ADDRESS;
}
mtd->priv = &nand_info;
printf( "Warning: After testing, Diagnostic will erase offset 0x20000 block.\n"
"This block storage U-boot Environment information.\n"
"You must re-enter `saveenv` in U-boot.\n");
#if defined(CONFIG_PC9223)
socle_scu_dev_enable(SOCLE_DEVCON_NFC);
#endif
#ifndef SKIP_AUTO_BOOT_TEST
if (autoboot_test () != 0)
printf("Auto Boot Up Test... [Fail]\n");
else
printf("Auto Boot Up Test... [Pass]\n");
#endif
socle_nand_initial_buf(BUFFER_INITIAL);
socle_nand_prepare_pattern((u8 *) TEST_PATTERN_TX_ADDR, TEST_PATTERN_BUF_SIZE);
socle_nfc_init();
/* Select the device */
socle_nfc_select_chip (mtd, 0);
if(nand_detect_flash(&socle_info))
return -1;
/* if (auto_boot_fail) {
printf("Auto Boot Up Test... [Fail]\n");
printf("Re-write page 0 for auto boot up test!!!\n");
socle_nfc_configure_timing(NULL, 0);
if(socle_nfc_block_erase(nand_info, 0)) {
printf("%s: Erase fail\n", __func__);
return -1;
}
if (socle_nfc_read_status(nand_info) & NAND_STATUS_FAIL) {
printf("%s: Read Status fail\n", __func__);
return -1;
}
nand_info->ecc_on = 0;
socle_nfc_set_ecc(nand_info);
socle_nand_initial_buf(BUFFER_WRITE);
if (!(socle_nfc_page_program_memory(nand_info, 0, nand_info->flash_info->page_size) & NAND_STATUS_READY)) {
printf("%s: Program Page fail\n", __func__);
return -1;
}
printf("Please power shut down and re-start diagnostic for auto boot test again!!!\n");
return -1;
}*/
socle_init_badblock_remap(nand_info);
nand_info->irq_on = 0;
ret = test_item_ctrl(&nfc_ctrl_feature_test_container, autotest);
return ret;
}
extern int
interrupt_test(int autotest)
{
#if 1
int ret = 0;
nand_info->irq_on = 1;
//socle_init_nfc_int(); //all interrupt, DMA, RnB, Protect
NDEBUG("Start Test Interrupt\n");
ret = test_item_ctrl(&nfc_ctrl_interrupt_test_container, autotest);
nand_info->irq_on = 0;
//socle_exit_nfc_int();
return ret;
#else
struct socle_nand_flash *flash_info = nand_info->flash_info;
int ret = 0;
u32 block_erase_num = 0;
socle_nfc_int_flag = 0;
socle_nfc_int_state = 0;
nand_info->dma_on = 0;
nand_info->ecc_on = 0;
socle_nfc_set_ecc(nand_info);
//test RnB interrupt
NDEBUG("------------Int test 1--------------------\n");
nand_info->dma_on = 1;
nand_info->dma_size= NF_DMA_SIZE_8;//NF_DMA_SIZE_16
nand_info->dma_mode = NF_DMA_BURST_8_ADDR_INC;
socle_nand_initial_buf(BUFFER_READ);
if (!(socle_nfc_interrupt_page_read(nand_info, NAND_TEST_PAGE_ADDR, flash_info->page_size) & NAND_STATUS_READY))
return -1;
free_irq(NAND_INT);
#if 0//def NFC_CTRL_DEBUG
show_data((u8 *)nand_info->buf_addr, 128);
show_data((u8 *)TEST_PATTERN_RX_ADDR, 128);
#endif
//compare
if(socle_nand_compare_pattern(TEST_PATTERN_RX_ADDR,nand_info->buf_addr, flash_info->page_size))
ret= -1;
//test Prot_IE interrupt
NDEBUG("------------Int test 2--------------------\n");
socle_nfc_set_protected_area(TEST_BEGIN_PROTECT_BLOCK, TEST_END_PROTECT_BLOCK);
socle_nand_initial_buf(BUFFER_WRITE);
if (!(socle_nfc_interrupt_page_program(nand_info, (TEST_BEGIN_PROTECT_BLOCK+1) *(flash_info->page_per_block),flash_info->page_size) & NAND_STATUS_WP))
ret = -1;
free_irq(NAND_INT);
NDEBUG(" Protect socle_nfc_int_state =0x%x\n",socle_nfc_int_state);
socle_nfc_set_protected_area(0, 0);
//Test DMA IE
NDEBUG("------------Int test 3--------------------\n");
nand_info->dma_on= 1;
nand_info->dma_size= NF_DMA_SIZE_8;//NF_DMA_SIZE_16
nand_info->dma_mode = NF_DMA_BURST_8_ADDR_INC;
if ((page_number %flash_info->page_per_block)==0)
{
block_erase_num = (int)(NAND_TEST_PAGE_ADDR + page_number)/flash_info->page_per_block;
NDEBUG("Block erase number = 0x%x\n", block_erase_num);
if(socle_nfc_block_erase(nand_info, block_erase_num))
return -1;
if (socle_nfc_read_status(nand_info) & NAND_STATUS_FAIL)
return -1;
page_number = 0;
}
page_number ++;
NDEBUG("===Int write page\n");
socle_nand_initial_buf(BUFFER_WRITE);
if (!(socle_nfc_dma_interrupt_page_program(nand_info, NAND_TEST_PAGE_ADDR + page_number, flash_info->page_size) & NAND_STATUS_READY))
return -1;
free_irq(NAND_INT);
NDEBUG("===Int read page\n");
socle_nand_initial_buf(BUFFER_READ);
if (!(socle_nfc_dma_interrupt_page_read(nand_info, NAND_TEST_PAGE_ADDR + page_number, flash_info->page_size) & NAND_STATUS_READY))
return -1;
free_irq(NAND_INT);
//compare
if(socle_nand_compare_pattern(TEST_PATTERN_TX_ADDR,TEST_PATTERN_RX_ADDR, nand_info->flash_info->page_size))
ret= -1;
socle_nfc_write(socle_nfc_read( NF_SFR_FLCTRL) &~ (NF_CTRL_INT_EN|NF_CTRL_ACC_ERR_EN|NF_CTRL_PROT_IE|NF_CTRL_RNB_IE|NF_CTRL_DMA_IE|NF_CTRL_DMA_TRIGGER|NF_CTRL_TRANS_COMPLETE) , NF_SFR_FLCTRL);
return ret;
#endif
}
