struct file * uart_console_open(struct stm32f_usart * us)
{
struct uart_console_dev * dev = &uart_console_dev;
DCC_LOG(LOG_INFO, "...");
dev->rx_flag = thinkos_flag_alloc();
#if ENABLE_UART_TX_BLOCK
dev->tx_flag = thinkos_flag_alloc();
#endif
#if ENABLE_UART_TX_MUTEX
dev->tx_mutex = thinkos_mutex_alloc();
#endif
uart_fifo_init(&dev->tx_fifo, UART_TX_FIFO_BUF_LEN);
uart_fifo_init(&dev->rx_fifo, UART_RX_FIFO_BUF_LEN);
dev->txie = CM3_BITBAND_DEV(&us->cr1, 7);
dev->uart = us;
cm3_irq_pri_set(STM32F_IRQ_USART1, UART_IRQ_PRIORITY);
cm3_irq_enable(STM32F_IRQ_USART1);
/* enable RX interrupt */
us->cr1 |= USART_RXNEIE | USART_IDLEIE;
return (struct file *)&uart_console_file;
}
int stm32f_serial_init(struct stm32f_serial_drv * drv,
unsigned int baudrate, unsigned int flags)
{
struct stm32_usart * uart = drv->uart;
DCC_LOG1(LOG_TRACE, "UART=0x%08x", uart);
DCC_LOG1(LOG_TRACE, "SERIAL_RX_FIFO_LEN=%d", SERIAL_RX_FIFO_LEN);
DCC_LOG1(LOG_TRACE, "SERIAL_TX_FIFO_LEN=%d", SERIAL_TX_FIFO_LEN);
DCC_LOG1(LOG_TRACE, "SERIAL_ENABLE_TX_MUTEX=%d", SERIAL_ENABLE_TX_MUTEX);
drv->rx_flag = thinkos_flag_alloc();
drv->tx_flag = thinkos_flag_alloc();
#if SERIAL_ENABLE_TX_MUTEX
drv->tx_mutex = thinkos_mutex_alloc();
DCC_LOG1(LOG_TRACE, "tx_mutex=%d", drv->tx_mutex);
#endif
drv->tx_fifo.head = drv->tx_fifo.tail = 0;
drv->rx_fifo.head = drv->rx_fifo.tail = 0;
drv->txie = CM3_BITBAND_DEV(&uart->cr1, 7);
thinkos_flag_give(drv->tx_flag);
stm32_usart_init(uart);
stm32_usart_baudrate_set(uart, baudrate);
stm32_usart_mode_set(uart, SERIAL_8N1);
/* enable RX interrupt */
uart->cr1 |= USART_RXNEIE | USART_IDLEIE;
/* enable UART */
stm32_usart_enable(uart);
return 0;
}
struct telnet_svc * telnet_svc_init(int port)
{
struct telnet_svc * tn = &telnet_svc;
int th;
if (port == 0)
port = 23; /* use default TELNET srvice port */
tn->svc = tcp_alloc();
tn->tp = NULL;
tcp_bind(tn->svc, INADDR_ANY, htons(port));
if (tcp_listen(tn->svc, 1) != 0) {
INF("Can't register the TCP listner!");
return NULL;
}
tn->rx.nonempty_flag = thinkos_flag_alloc();
tn->rx.nonfull_flag = thinkos_flag_alloc();
tn->rx.head = 0;
tn->rx.tail = 0;
th = thinkos_thread_create_inf((void *)telnet_input_task, (void *)tn,
&telnet_srv_inf);
(void)th;
INF("TELNET TCP input thread=%d", th);
return tn;
}
int net_init(void)
{
tracef("%s():...", __func__);
if (lattice_ice40_configure(ice40lp384_bin, sizeof_ice40lp384_bin) < 0) {
trace("lattice_ice40_configure() failed!");
return -1;
}
/* IO init */
stm32_gpio_mode(RS485_RX, ALT_FUNC, PULL_UP);
stm32_gpio_af(RS485_RX, GPIO_AF7);
stm32_gpio_mode(RS485_TX, ALT_FUNC, PUSH_PULL | SPEED_MED);
stm32_gpio_af(RS485_TX, GPIO_AF7);
#ifdef RS485_CK
stm32_gpio_mode(RS485_CK, ALT_FUNC, PUSH_PULL | SPEED_MED);
stm32_gpio_af(RS485_CK, GPIO_AF7);
#endif
#ifdef RS485_TRIG
stm32_gpio_mode(RS485_TRIG, INPUT, PULL_UP);
#endif
#ifdef RS485_TXEN
stm32_gpio_mode(RS485_TXEN, OUTPUT, PUSH_PULL | SPEED_MED);
stm32_gpio_set(RS485_TXEN);
#endif
#ifdef RS485_LOOP
stm32_gpio_mode(RS485_LOOP, OUTPUT, PUSH_PULL | SPEED_MED);
stm32_gpio_set(RS485_LOOP);
#endif
#ifdef RS485_MODE
stm32_gpio_mode(RS485_MODE, OUTPUT, PUSH_PULL | SPEED_LOW);
stm32_gpio_set(RS485_MODE);
#endif
if (!net.initialized) {
/* Link init */
rs485_init(&net.link, RS485_USART, RS485_LINK_SPEED,
USART1_DMA, USART1_DMA_CHAN,
USART1_RX_DMA_STRM, USART1_TX_DMA_STRM);
/* initialize the packet buffer pool */
pktbuf_pool_init();
net_recv_init();
net.probe_flag = thinkos_flag_alloc();
net.initialized = true;
}
return 0;
}
void i2c_master_init(unsigned int scl_freq)
{
struct stm32f_i2c * i2c = STM32F_I2C1;
struct stm32f_rcc * rcc = STM32F_RCC;
uint32_t pclk = stm32f_apb1_hz;
#if defined(STM32F1X)
struct stm32f_afio * afio = STM32F_AFIO;
/* Use alternate pins for I2C1 */
afio->mapr |= AFIO_I2C1_REMAP;
#endif
stm32f_gpio_mode(I2C1_SCL, ALT_FUNC, OPEN_DRAIN);
stm32f_gpio_mode(I2C1_SDA, ALT_FUNC, OPEN_DRAIN);
#if defined(STM32F4X)
stm32f_gpio_af(I2C1_SCL, GPIO_AF4);
stm32f_gpio_af(I2C1_SDA, GPIO_AF4);
#endif
/* Enable I2C clock */
rcc->apb1enr |= RCC_I2C1EN;
/* Software reset */
i2c->cr1 = I2C_SWRST;
DCC_LOG3(LOG_TRACE, "CR1=0x%04x CR2=0x%04x CCR=0x%04x",
i2c->cr1, i2c->cr2, i2c->ccr);
DCC_LOG3(LOG_TRACE, "OAR1=0x%04x OAR2=0x%04x TRISE=0x%04x",
i2c->oar1, i2c->oar2, i2c->trise);
DCC_LOG2(LOG_TRACE, "SR1=0x%04x SR2=0x%04x ", i2c->sr1, i2c->sr2);
i2c->cr1 = 0;
/* I2C Control register 2 (I2C_CR2) */
i2c->cr2 = I2C_FREQ_SET(pclk / 1000000);
/* I2C Own address register 1 (I2C_OAR1) */
i2c->oar1 = 0;
/* I2C Own address register 2 (I2C_OAR2) */
i2c->oar2 = 0;
/* I2C Clock control register (I2C_CCR) */
i2c->ccr = I2C_CCR_SET(pclk / scl_freq / 2);
/* I2C TRISE register (I2C_TRISE) */
i2c->trise = I2C_TRISE_SET((pclk / 1000000) + 1);
xfer.flag = thinkos_flag_alloc();
cm3_irq_enable(STM32F_IRQ_I2C1_EV);
/* set event IRQ to very high priority */
cm3_irq_pri_set(STM32F_IRQ_DMA1_STREAM0, I2C_IRQ_PRIORITY);
cm3_irq_enable(STM32F_IRQ_I2C1_ER);
/* set error IRQ to high priority */
cm3_irq_pri_set(STM32F_IRQ_DMA1_STREAM0, I2C_IRQ_PRIORITY);
DCC_LOG(LOG_TRACE, "Enabling interrupts....");
/* enable ACK, events and errors */
i2c->cr2 |= I2C_ITERREN | I2C_ITEVTEN | I2C_ITBUFEN;
}
void leds_init(void)
{
struct stm32_rcc * rcc = STM32_RCC;
struct stm32f_tim * tim = STM32F_TIM3;
struct stm32_afio * afio = STM32_AFIO;
uint32_t div;
uint32_t pre;
uint32_t n;
afio->mapr |= AFIO_SPI1_REMAP;
stm32_gpio_mode(LED1_IO, ALT_FUNC, PUSH_PULL | SPEED_HIGH);
stm32_gpio_mode(LED2_IO, ALT_FUNC, PUSH_PULL | SPEED_HIGH);
/* get the total divisior */
div = ((2 * stm32f_apb1_hz) + (TIMER_PWM_FREQ / 2)) / TIMER_PWM_FREQ;
/* get the minimum pre scaler */
pre = (div / 65536) + 1;
/* get the reload register value */
n = (div + pre / 2) / pre;
DCC_LOG2(LOG_TRACE, "div=%d pre=%d", div, pre);
/* Timer clock enable */
rcc->apb1enr |= RCC_TIM3EN;
/* Timer configuration */
tim->sr= 0; /* Clear interrupts */
tim->psc = pre - 1;
tim->arr = n - 1;
tim->cnt = 0;
tim->egr = 0;
tim->rcr = 0;
/* */
DCC_LOG1(LOG_TRACE, "ARR=%d", tim->arr);
tim->ccr1 = 0;
tim->ccr2 = tim->arr;
tim->ccmr1 = TIM_OC1M_PWM_MODE1 | TIM_OC1PE | \
TIM_OC2M_PWM_MODE2 | TIM_OC2PE;
tim->ccer = TIM_CC1E | TIM_CC2E;
tim->bdtr = TIM_MOE | TIM_OSSR;
/* enable counter */
tim->cr2 = 0;
tim->cr1 = TIM_URS | TIM_CEN;
led_flag = thinkos_flag_alloc();
thinkos_thread_create((void *)led_task, (void *)NULL,
led_stack, sizeof(led_stack) |
THINKOS_OPT_PRIORITY(8) | THINKOS_OPT_ID(6));
}
usb_cdc_class_t * usb_cdc_init(const usb_dev_t * usb,
const uint8_t * const str[],
unsigned int strcnt)
{
struct usb_cdc_acm_dev * dev = &usb_cdc_rt;
usb_class_t * cl = (usb_class_t *)dev;
/* initialize USB device */
dev->usb = (usb_dev_t *)usb;
#ifndef CDC_RX_SEM_NO
dev->rx_sem = thinkos_sem_alloc(0);
#endif
#ifndef CDC_TX_DONE_NO
dev->tx_done = thinkos_flag_alloc();
#endif
#ifndef CDC_TX_LOCK_NO
dev->tx_lock = thinkos_flag_alloc();
#endif
#ifndef CDC_CTL_FLAG_NO
dev->ctl_flag = thinkos_flag_alloc();
#endif
dev->rx_cnt = 0;
dev->rx_pos = 0;
dev->str = str;
dev->strcnt = strcnt;
DCC_LOG4(LOG_INFO, "tx_done=%d tx_lock=%d rx_sem=%d ctl_flag=%d",
TX_DONE, TX_LOCK, RX_SEM, CTL_FLAG);
thinkos_flag_clr(TX_DONE);
thinkos_flag_clr(TX_LOCK);
thinkos_flag_clr(CTL_FLAG);
usb_dev_init(dev->usb, cl, &usb_cdc_ev);
return (usb_cdc_class_t *)dev;
}
/***********************************************************
ADC Configuration
***********************************************************/
void stm32f_adc_init(void)
{
struct stm32_rcc * rcc = STM32_RCC;
struct stm32f_adc * adc = STM32F_ADC1;
const uint8_t adc_chan_seq[] = {6, 18, 6};
#ifdef STM32F_ADCC
struct stm32f_adcc * adcc = STM32F_ADCC;
/* Common Control */
adcc->ccr = ADC_TSVREFE | ADC_VBATE | ADC_ADCPRE_4;
/* PCLK2 = 60MHz
ADCCLK = PCLK2/4 = 15MHz */
#endif
/* ADC clock enable */
rcc->apb2enr |= RCC_ADC1EN;
/* configure for DMA use, select timer2 trigger */
adc->cr1 = ADC_RES_12BIT | ADC_SCAN;
adc->cr2 = ADC_EXTEN_RISING | ADC_EXTSEL_TIM2_TRGO | ADC_ADON |
ADC_DDS | ADC_DMA;
/* Chan 6 is external
Chan 18 is the battery (VBAT)
Chan 16 is the internal temperature sensor */
stm32f_adc_seq_set(adc, adc_chan_seq, 3);
/* set the sample time */
stm32f_adc_smp_set(adc, 6, ADC_SMP_56_CYC);
stm32f_adc_smp_set(adc, 18, ADC_SMP_56_CYC);
stm32f_adc_smp_set(adc, 16, ADC_SMP_56_CYC);
adc_gpio_init();
adc_dma2_init(adc_buf[0], adc_buf[1], (void *)&adc->dr, ADC_CHANS);
#if (ENABLE_ADC_SYNC)
/* synchronization event */
adc_dma_sync = thinkos_flag_alloc();
#endif
/* Set DMA to very low priority */
cm3_irq_pri_set(STM32F_IRQ_DMA2_STREAM0, 0xf0);
/* Enable DMA interrupt */
cm3_irq_enable(STM32F_IRQ_DMA2_STREAM0);
/* Configure timer and start periodic conversion */
adc_tim2_init(ADC_RATE);
}
void i2s_slave_init(void)
{
struct stm32f_spi * spi = STM32F_SPI2;
struct stm32f_spi * i2s_ext = STM32F_I2S2EXT;
struct stm32f_rcc * rcc = STM32F_RCC;
struct stm32f_dma * dma = STM32F_DMA1;
tracef("%s SPI=0x%08x", __func__, (uint32_t)spi);
tracef("%s I2S_EXT=0X%08x", __func__, (uint32_t)i2s_ext);
stm32f_gpio_af(I2S2_WS, GPIO_AF5);
stm32f_gpio_af(I2S2_CK, GPIO_AF5);
stm32f_gpio_af(I2S2EXT_SD, GPIO_AF6);
stm32f_gpio_af(I2S2_SD, GPIO_AF5);
/* DMA clock enable */
rcc->ahb1enr |= RCC_DMA1EN;
DCC_LOG(LOG_TRACE, "1.");
/* Disable DMA channel */
dma->s[I2S_DMA_RX_STRM].cr = 0;
while (dma->s[I2S_DMA_RX_STRM].cr & DMA_EN);
dma->s[I2S_DMA_TX_STRM].cr = 0;
while (dma->s[I2S_DMA_TX_STRM].cr & DMA_EN);
DCC_LOG(LOG_TRACE, "2.");
/* Enable SPI clock */
rcc->apb1enr |= RCC_SPI2EN;
/* disable peripherals */
spi->i2scfgr &= ~SPI_I2SE;
i2s_ext->i2scfgr &= ~SPI_I2SE;
spi->cr1 = 0;
spi->cr2 = 0;
spi->i2scfgr = SPI_I2SMOD | SPI_I2SCFG_SLV_RCV |
SPI_PCMSYNC_SHORT | SPI_I2SSTD_PCM | SPI_DATLEN_16 | SPI_CHLEN_16;
spi->i2spr = 0;
spi->cr2 = SPI_RXDMAEN;
DCC_LOG(LOG_TRACE, "3.");
i2s_ext->cr1 = 0;
i2s_ext->cr2 = 0;
i2s_ext->i2scfgr = SPI_I2SMOD | SPI_I2SCFG_SLV_XMT |
SPI_PCMSYNC_SHORT | SPI_I2SSTD_PCM | SPI_DATLEN_16 | SPI_CHLEN_16;
i2s_ext->i2spr = 0;
i2s_ext->cr2 = SPI_TXDMAEN;
DCC_LOG(LOG_TRACE, "4.");
i2s.tx.buf[0] = (sndbuf_t *)&sndbuf_zero;
i2s.tx.buf[1] = (sndbuf_t *)&sndbuf_zero;
i2s.tx.idx = 0;
i2s.rx.buf[0] = &sndbuf_null;
i2s.rx.buf[1] = &sndbuf_null;
i2s.rx.idx = 0;
/* Configure DMA channel */
dma->s[I2S_DMA_RX_STRM].cr = DMA_CHSEL_SET(I2S_DMA_RX_CHAN) |
DMA_MBURST_1 | DMA_PBURST_1 | DMA_MSIZE_16 | DMA_PSIZE_16 |
DMA_CT_M0AR | DMA_DBM | DMA_CIRC | DMA_MINC | DMA_DIR_PTM |
DMA_TCIE | DMA_TEIE | DMA_DMEIE;
dma->s[I2S_DMA_RX_STRM].par = &spi->dr;
dma->s[I2S_DMA_RX_STRM].m0ar = i2s.rx.buf[0]->data;
i2s.rx.xfr[0] = i2s.rx.buf[0];
dma->s[I2S_DMA_RX_STRM].m1ar = i2s.rx.buf[1]->data;
i2s.rx.xfr[1] = i2s.rx.buf[1];
dma->s[I2S_DMA_RX_STRM].ndtr = SNDBUF_LEN;
dma->s[I2S_DMA_RX_STRM].fcr = DMA_FEIE | DMA_DMDIS | DMA_FTH_FULL;
DCC_LOG(LOG_TRACE, "5.");
dma->s[I2S_DMA_TX_STRM].cr = DMA_CHSEL_SET(I2S_DMA_TX_CHAN) |
DMA_MBURST_1 | DMA_PBURST_1 | DMA_MSIZE_16 | DMA_PSIZE_16 |
DMA_CT_M0AR | DMA_DBM | DMA_CIRC | DMA_MINC | DMA_DIR_MTP |
DMA_TCIE | DMA_TEIE | DMA_DMEIE;
dma->s[I2S_DMA_RX_STRM].par = &spi->dr;
dma->s[I2S_DMA_TX_STRM].par = &i2s_ext->dr;
dma->s[I2S_DMA_TX_STRM].m0ar = i2s.tx.buf[0]->data;
dma->s[I2S_DMA_TX_STRM].m1ar = i2s.tx.buf[1]->data;
dma->s[I2S_DMA_TX_STRM].ndtr = SNDBUF_LEN;
dma->s[I2S_DMA_TX_STRM].fcr = DMA_FEIE | DMA_DMDIS | DMA_FTH_FULL;
DCC_LOG(LOG_TRACE, "6.");
/* Set DMA to medium priority */
cm3_irq_pri_set(I2S_DMA_RX_IRQ, 0x10);
cm3_irq_enable(I2S_DMA_RX_IRQ);
DCC_LOG(LOG_TRACE, "7.");
cm3_irq_pri_set(I2S_DMA_TX_IRQ, 0x10);
cm3_irq_enable(I2S_DMA_TX_IRQ);
DCC_LOG(LOG_TRACE, "8.");
i2s.io_flag = thinkos_flag_alloc();
tracef("%s(): flag=%d.", __func__, i2s.io_flag);
}
