static int ti_pipe3_suspend(struct device *dev) { struct ti_pipe3 *phy = dev_get_drvdata(dev); ti_pipe3_disable_clocks(phy); return 0; }
static int ti_pipe3_exit(struct phy *x) { struct ti_pipe3 *phy = phy_get_drvdata(x); u32 val; unsigned long timeout; /* If dpll_reset_syscon is not present we wont power down SATA DPLL * due to Errata i783 */ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") && !phy->dpll_reset_syscon) return 0; if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { /* Put DPLL in IDLE mode */ val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val |= PLL_IDLE; ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); /* wait for LDO and Oscillator to power down */ timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME); do { cpu_relax(); val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) break; } while (!time_after(jiffies, timeout)); if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", val); return -EBUSY; } } /* i783: SATA needs control bit toggle after PLL unlock */ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) { regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET); regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, SATA_PLL_SOFT_RESET, 0); } ti_pipe3_disable_clocks(phy); return 0; }