/** @brief DMA2,3 callback
*
* callback function for DMA transfer
*/
void dma1_channel2_3_isr( void )
{
/* after DMA transfer completed enable timer 3 overflow */
dma_clear_interrupt_flags(DMA1, DMA_CHANNEL2, DMA_TCIF);
timer_enable_irq(TIM3, TIM_DIER_UIE);
dma_disable_channel( DMA1, DMA_CHANNEL2);
dma_disable_channel( DMA1, DMA_CHANNEL3);
dma_disable_channel( DMA1, DMA_CHANNEL4);
timer_disable_irq( TIM3, TIM_DIER_CC1DE);
timer_disable_irq( TIM3, TIM_DIER_CC3DE);
timer_disable_irq( TIM3, TIM_DIER_UDE);
}
/* TIM2 Interrupt Handler gets executed on every TIM2 Update if enabled */
void TIM2_IRQHandler(void)
{
// Clear TIM2 Interrupt Flag
TIMER2->regs.gen->SR &= ~TIMER_SR_UIF;
/* check if certain number of overflows has occured yet
* this ISR is used to guarantee a 50us dead time on the data lines
* before another frame is transmitted */
if (TIM2_overflows < (uint8_t)WS2812_DEADPERIOD)
{
// count the number of occured overflows
TIM2_overflows++;
}
else
{
// clear the number of overflows
TIM2_overflows = 0;
// stop TIM2 now because dead period has been reached
timer_pause(TIMER2);
/* disable the TIM2 Update interrupt again
* so it doesn't occur while transmitting data */
timer_disable_irq(TIMER2, TIMER_UPDATE_INTERRUPT);
// finally indicate that the data frame has been transmitted
WS2812_TC = 1;
}
}
/**
* Initialize the DSM timer
*/
static void timer_dsm_init(void) {
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
// Enable the timer NVIC
nvic_enable_irq(TIMER_DSM_NVIC);
nvic_set_priority(TIMER_DSM_NVIC, 1);
// Setup the timer
timer_disable_counter(TIMER_DSM);
timer_reset(TIMER_DSM);
timer_set_mode(TIMER_DSM, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_disable_preload(TIMER_DSM);
timer_continuous_mode(TIMER_DSM);
// Disable interrupts on Compare 1
timer_disable_irq(TIMER_DSM, TIM_DIER_CC1IE);
// Clear the Output Compare of OC1
timer_disable_oc_clear(TIMER_DSM, TIM_OC1);
timer_disable_oc_preload(TIMER_DSM, TIM_OC1);
timer_set_oc_slow_mode(TIMER_DSM, TIM_OC1);
timer_set_oc_mode(TIMER_DSM, TIM_OC1, TIM_OCM_FROZEN);
// Set timer updates each 10 microseconds
#if DEBUG && !DSM_RECEIVER && !DSM_MITM
timer_set_prescaler(TIMER_DSM, 720000 - 1);
#else
timer_set_prescaler(TIMER_DSM, 720 - 1);
#endif
timer_set_period(TIMER_DSM, 65535);
// Start the timer
timer_enable_counter(TIMER_DSM);
}
void pwm_mode(timer_dev *dev, uint8_t channel) {
timer_disable_irq(dev, channel);
// timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE);
switch (channel)
{
case 1:
TIM_SelectOCxM(dev->regs, TIM_Channel_1, TIM_OCMode_PWM1);
TIM_OC1PreloadConfig(dev->regs, TIM_OCPreload_Enable);
break;
case 2:
TIM_SelectOCxM(dev->regs, TIM_Channel_2, TIM_OCMode_PWM1);
TIM_OC2PreloadConfig(dev->regs, TIM_OCPreload_Enable);
break;
case 3:
TIM_SelectOCxM(dev->regs, TIM_Channel_3, TIM_OCMode_PWM1);
TIM_OC3PreloadConfig(dev->regs, TIM_OCPreload_Enable);
break;
case 4:
TIM_SelectOCxM(dev->regs, TIM_Channel_4, TIM_OCMode_PWM1);
TIM_OC4PreloadConfig(dev->regs, TIM_OCPreload_Enable);
break;
}
timer_cc_enable(dev, channel);
}
/* Function to stop a timer */
void timer_stop(void)
{
/* counter disable */
timer_disable_counter(TIM2);
/* disable update interrupt */
timer_disable_irq(TIM2, TIM_DIER_UIE);
}
void tim7_isr(void)
{
timer_clear_flag(TIM7, TIM_SR_UIF);
state.rht_timeout = true;
nvic_disable_irq(NVIC_TIM7_IRQ);
timer_disable_irq(TIM7, TIM_DIER_UIE);
timer_disable_counter(TIM7);
}
void tim2_isr(void)
{
gpio_toggle(GPIOB, GPIO8); /* LED2 on/off. */
if (timer_get_flag(TIM2, TIM_SR_UIF))
timer_clear_flag(TIM2, TIM_SR_UIF); /* Clear interrrupt flag. */
timer_get_flag(TIM2, TIM_SR_UIF); /* Reread to force the previous write */
timer_disable_irq(TIM2, TIM_DIER_UIE);
timer_disable_counter(TIM2);
}
void PPMin_TIM_Init()
{
/* Enable TIM1 clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
/* No Enable TIM1 interrupt. */
// nvic_enable_irq(NVIC_TIM1_IRQ);
// nvic_set_priority(NVIC_TIM1_IRQ, 16); //High priority
/* Reset TIM1 peripheral. */
timer_disable_counter(TIM1);
timer_reset(TIM1);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value. timer updates each uSecond */
timer_set_prescaler(TIM1, PPMIn_prescaler); // uSecond (72MHz / (35+1) = 2MHz = 0.5uSecond
timer_set_period(TIM1, PPMIn_period); // 3300uSecond= 2MHz*6600times, TIM1_prescaler=0.5uSecond
/* Disable preload. */
timer_disable_preload(TIM1);
/* Continous mode. */
timer_continuous_mode(TIM1);
/* Disable outputs. */
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
/* Enable CCP1 */
timer_disable_oc_clear(TIM1, TIM_OC1);
timer_disable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_slow_mode(TIM1, TIM_OC1);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
/* Enable commutation interrupt. */
// timer_enable_irq(TIM1, TIM_DIER_CC1IE);
/* Disable CCP1 interrupt. */
timer_disable_irq(TIM1, TIM_DIER_CC1IE);
/* Counter enable. */
timer_disable_counter(TIM1);
}
/*
* Runs deferred processing for usb uart rx, draining RX FIFO by sending
* characters to host PC via CDCACM. Allowed to read from FIFO in pointer,
* but not write to it. Allowed to write to FIFO out pointer.
*/
static void usbuart_run(void)
{
/* forcibly empty fifo if no USB endpoint */
if (cdcacm_get_config() != 1)
{
buf_rx_out = buf_rx_in;
}
/* if fifo empty, nothing further to do */
if (buf_rx_in == buf_rx_out) {
/* turn off LED, disable IRQ */
timer_disable_irq(USBUSART_TIM, TIM_DIER_UIE);
gpio_clear(LED_PORT_UART, LED_UART);
}
else
{
uint8_t packet_buf[CDCACM_PACKET_SIZE];
uint8_t packet_size = 0;
uint8_t buf_out = buf_rx_out;
/* copy from uart FIFO into local usb packet buffer */
while (buf_rx_in != buf_out && packet_size < CDCACM_PACKET_SIZE)
{
packet_buf[packet_size++] = buf_rx[buf_out++];
/* wrap out pointer */
if (buf_out >= FIFO_SIZE)
{
buf_out = 0;
}
}
/* advance fifo out pointer by amount written */
buf_rx_out += usbd_ep_write_packet(usbdev,
CDCACM_UART_ENDPOINT, packet_buf, packet_size);
buf_rx_out %= FIFO_SIZE;
}
}
/** @brief Timer3 callback
*
* callback function for Timer3
*/
void tim3_isr(void)
{
uint8_t *bftemp;
timer_clear_flag(TIM3, TIM_SR_UIF);
/* wait an amount of time to trigger the WS2812 sync pulse */
if( waitcnt < NR_OF_WAITCOUNTS)
{
waitcnt++;
}
else
{
waitcnt = 0;
timer_disable_counter(TIM3);
timer_disable_irq(TIM3, TIM_DIER_UIE);
/* if new framebuffer data is available
* switch the unrolled buffer with the backbuffer
*/
if(update_flag == 1)
{
bftemp = actual_bitframe;
actual_bitframe = drawing_bitframe;
drawing_bitframe = bftemp;
update_flag = 0;
}
/* restart the sending process */
ws2812_send();
}
}
void disable_event_timer() {
timer_disable_irq(TIM2, TIM_DIER_CC1IE);
timer_clear_flag(TIM2, TIM_SR_CC1IF);
}
static void pwm_mode(timer_dev *dev, uint8 channel) {
timer_disable_irq(dev, channel);
timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE);
timer_cc_enable(dev, channel);
}
/**
* @brief Detach a timer interrupt.
* @param dev Timer device
* @param interrupt Interrupt number to detach; this may be any
* timer_interrupt_id or timer_channel value appropriate
* for the timer.
* @see timer_interrupt_id
* @see timer_channel
*/
void timer_detach_interrupt(timer_dev *dev, uint8 interrupt) {
timer_disable_irq(dev, interrupt);
dev->handlers[interrupt] = NULL;
}
/**
* Stop the DSM timer interrupts
*/
void timer_dsm_stop(void) {
// Clear the interrupt flag and disable the interrupt of compare 1
timer_clear_flag(TIMER_DSM, TIM_SR_CC1IF);
timer_disable_irq(TIMER_DSM, TIM_DIER_CC1IE);
}
/* ----------------------- Disable timer -----------------------------*/
inline void
vMBPortTimersDisable( )
{
timer_disable_irq(TIM2, TIM_DIER_UIE);
timer_disable_counter(TIM2);
}
