示例#1
0
void plc_wait_tmr_init(void)
{
    //Wait timer config, basic timers TIM6 and TIM7 may be used
    rcc_periph_clock_enable( PLC_WAIT_TMR_PERIPH );

    timer_reset            ( PLC_WAIT_TMR );
    timer_set_prescaler    ( PLC_WAIT_TMR, ((2*rcc_apb1_frequency)/1000000ul - 1)); //1MHz
    timer_disable_preload  ( PLC_WAIT_TMR );
    timer_continuous_mode  ( PLC_WAIT_TMR );
    timer_set_period       ( PLC_WAIT_TMR, 1000 ); //1KHz

    timer_enable_counter   ( PLC_WAIT_TMR );
    timer_enable_irq       ( PLC_WAIT_TMR, TIM_DIER_UIE);

    nvic_enable_irq( PLC_WAIT_TMR_VECTOR );
}
示例#2
0
/* timer add */
timeval_t
timer_add_long(timeval_t a, long b)
{
	timeval_t ret;

	timer_reset(ret);
	ret.tv_usec = a.tv_usec + b % TIMER_HZ;
	ret.tv_sec = a.tv_sec + b / TIMER_HZ;

	if (ret.tv_usec >= TIMER_HZ) {
		ret.tv_sec++;
		ret.tv_usec -= TIMER_HZ;
	}

	return ret;
}
示例#3
0
/* timer sub */
timeval_t
timer_sub(timeval_t a, timeval_t b)
{
	timeval_t ret;

	timer_reset(ret);
	ret.tv_usec = a.tv_usec - b.tv_usec;
	ret.tv_sec = a.tv_sec - b.tv_sec;

	if (ret.tv_usec < 0) {
		ret.tv_usec += TIMER_HZ;
		ret.tv_sec--;
	}

	return ret;
}
示例#4
0
/*---------------------------------------------------------------------------*/
void
httpd_appcall(void *state)
{
  struct httpd_state *s = (struct httpd_state *)state;

  if(uip_closed() || uip_aborted() || uip_timedout()) {
    if(s != NULL) {
      if(s->fd >= 0) {
        cfs_close(s->fd);
	s->fd = -1;
      }
      memb_free(&conns, s);
    }
  } else if(uip_connected()) {
    s = (struct httpd_state *)memb_alloc(&conns);
    if(s == NULL) {
      uip_abort();
      webserver_log_file(&uip_conn->ripaddr, "reset (no memory block)");
      return;
    }
    tcp_markconn(uip_conn, s);
    PSOCK_INIT(&s->sin, (uint8_t *)s->inputbuf, sizeof(s->inputbuf) - 1);
    PSOCK_INIT(&s->sout, (uint8_t *)s->inputbuf, sizeof(s->inputbuf) - 1);
    PT_INIT(&s->outputpt);
    s->fd = -1;
    s->state = STATE_WAITING;
    timer_set(&s->timer, CLOCK_SECOND * 10);
    handle_connection(s);
  } else if(s != NULL) {
    if(uip_poll()) {
      if(timer_expired(&s->timer)) {
	uip_abort();
	if(s->fd >= 0) {
	  cfs_close(s->fd);
	  s->fd = -1;
	}
        memb_free(&conns, s);
        webserver_log_file(&uip_conn->ripaddr, "reset (timeout)");
      }
    } else {
      timer_reset(&s->timer);
    }
    handle_connection(s);
  } else {
    uip_abort();
  }
}
示例#5
0
void TCPIP_TCPIPTask(void)
{
	if (timer_expired(&Periodic_Timer))
	{
		timer_reset(&Periodic_Timer);
		
		Debug_PrintChar('*');
		
		for (uint8_t i = 0; i < UIP_CONNS; i++)
		{
	 		uip_periodic(i);
	 		 
	 		if (uip_len > 0)													// If the above function invocation resulted in data that should be sent out on the network,
			  network_send(IP);												//the global variable uip_len is set to a value > 0.
		}
	}
}
示例#6
0
bool __timer_timeout_helper(bool cond)
{
    if(timer_reached() || !cond)
    {
        timerstack_count--;
        if(timerstack_count == 0)
            timer_reset();
        else if (timerstack_count <= TIMER_STACK_SIZE)
        {
            if(timerstack[timerstack_count-1] != 0)
                timer_set(timer_remaining()+timerstack[timerstack_count-1]);
        }
        return false;
    }
    else
        return true;
}
示例#7
0
int main()
{
	int i, rc, len, ffd;

	ffd = open("myfifo", O_RDWR | O_NONBLOCK);
	if (ffd == -1)
	{
		perror("cannot open fifo");
		return -1;
	}

	printf("writing fifo...\n");

	struct timer t;
	timer_reset(&t);

	const int N = 1000000;
	int errors = 0;
	char buf[1024];
	len = sprintf(buf, "01234567890123456789012345678901234567890123456789");

	for (i = 0; i < N; i++)
	{
		do
		{
			rc = write(ffd, buf, len);
			if (rc == -1)
			{
				errors++;
				usleep(2000);
			}
		}
		while (rc == -1);

		if (rc != len)
		{
			perror("cannot write to fifo");
			break;
		}
	}

	timer_print_elapsed("fifo_write", i, &t);
	printf("errors: %d\n", errors);

	return 0;
}
static void
fifo_output_cancel(void *data)
{
	struct fifo_data *fd = (struct fifo_data *)data;
	char buf[FIFO_BUFFER_SIZE];
	int bytes = 1;

	timer_reset(fd->timer);

	while (bytes > 0 && errno != EINTR)
		bytes = read(fd->input, buf, FIFO_BUFFER_SIZE);

	if (bytes < 0 && errno != EAGAIN) {
		g_warning("Flush of FIFO \"%s\" failed: %s",
			  fd->path, strerror(errno));
	}
}
示例#9
0
int test_timerprint()
{
    TimerData timer;
    timer_reset(&timer);
    timer_init();
    double time = timer_print(&timer);
    if (time != 0)
        goto fail;
    uint64_t cycles = timer_printCycles(&timer);
    if (cycles != 0)
        goto fail;
    timer_finalize();
    return 1;
fail:
    timer_finalize();
    return 0;
}
示例#10
0
/*
 * timer_tick()
 *	Kernel system timer support. Needs to keep up the real-time clock,
 * 	as well as call the "do_timer()" routine every clocktick.
 */
static irqreturn_t timer_tick(int irq, void *dummy)
{
	int ticks;

	BUG_ON(!irqs_disabled());
	ticks = timer_reset(timervector, frequency);

	xtime_update(ticks);

	update_process_times(user_mode(get_irq_regs()));
	profile_tick(CPU_PROFILING);

#if defined(CONFIG_SMP)
	smp_send_timer_all();
#endif
	return(IRQ_HANDLED);
}
示例#11
0
void usbuart_init(void)
{
#if defined(BLACKMAGIC)
	/* On mini hardware, UART and SWD share connector pins.
	 * Don't enable UART if we're being debugged. */
	if ((platform_hwversion() == 1) && (SCS_DEMCR & SCS_DEMCR_TRCENA))
		return;
#endif

	rcc_peripheral_enable_clock(&USBUSART_APB_ENR, USBUSART_CLK_ENABLE);

	UART_PIN_SETUP();

	/* Setup UART parameters. */
	usart_set_baudrate(USBUSART, 38400);
	usart_set_databits(USBUSART, 8);
	usart_set_stopbits(USBUSART, USART_STOPBITS_1);
	usart_set_mode(USBUSART, USART_MODE_TX_RX);
	usart_set_parity(USBUSART, USART_PARITY_NONE);
	usart_set_flow_control(USBUSART, USART_FLOWCONTROL_NONE);

	/* Finally enable the USART. */
	usart_enable(USBUSART);

	/* Enable interrupts */
	USBUSART_CR1 |= USART_CR1_RXNEIE;
	nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART);
	nvic_enable_irq(USBUSART_IRQ);

	/* Setup timer for running deferred FIFO processing */
	USBUSART_TIM_CLK_EN();
	timer_reset(USBUSART_TIM);
	timer_set_mode(USBUSART_TIM, TIM_CR1_CKD_CK_INT,
			TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
	timer_set_prescaler(USBUSART_TIM,
			rcc_ppre2_frequency / USBUART_TIMER_FREQ_HZ * 2 - 1);
	timer_set_period(USBUSART_TIM,
			USBUART_TIMER_FREQ_HZ / USBUART_RUN_FREQ_HZ - 1);

	/* Setup update interrupt in NVIC */
	nvic_set_priority(USBUSART_TIM_IRQ, IRQ_PRI_USBUSART_TIM);
	nvic_enable_irq(USBUSART_TIM_IRQ);

	/* turn the timer on */
	timer_enable_counter(USBUSART_TIM);
}
示例#12
0
static void platform_init_eventtimer() {
  /* Set up TIM2 as 32bit clock */
  timer_reset(TIM2);
  timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
  timer_set_period(TIM2, 0xFFFFFFFF);
  timer_set_prescaler(TIM2, 0);
  timer_disable_preload(TIM2);
  timer_continuous_mode(TIM2);
  /* Setup output compare registers */
  timer_disable_oc_output(TIM2, TIM_OC1);
  timer_disable_oc_output(TIM2, TIM_OC2);
  timer_disable_oc_output(TIM2, TIM_OC3);
  timer_disable_oc_output(TIM2, TIM_OC4);
  timer_disable_oc_clear(TIM2, TIM_OC1);
  timer_disable_oc_preload(TIM2, TIM_OC1);
  timer_set_oc_slow_mode(TIM2, TIM_OC1);
  timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
  /* Setup input captures for CH2-4 Triggers */
  gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO3);
  gpio_set_af(GPIOB, GPIO_AF1, GPIO3);
  timer_ic_set_input(TIM2, TIM_IC2, TIM_IC_IN_TI2);
  timer_ic_set_filter(TIM2, TIM_IC2, TIM_IC_CK_INT_N_2);
  timer_ic_set_polarity(TIM2, TIM_IC2, TIM_IC_FALLING);
  timer_ic_enable(TIM2, TIM_IC2);

  gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO10);
  gpio_set_af(GPIOB, GPIO_AF1, GPIO10);
  timer_ic_set_input(TIM2, TIM_IC3, TIM_IC_IN_TI3);
  timer_ic_set_filter(TIM2, TIM_IC3, TIM_IC_CK_INT_N_2);
  timer_ic_set_polarity(TIM2, TIM_IC3, TIM_IC_FALLING);
  timer_ic_enable(TIM2, TIM_IC3);

  gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
  gpio_set_af(GPIOB, GPIO_AF1, GPIO11);
  timer_ic_set_input(TIM2, TIM_IC4, TIM_IC_IN_TI4);
  timer_ic_set_filter(TIM2, TIM_IC4, TIM_IC_CK_INT_N_2);
  timer_ic_set_polarity(TIM2, TIM_IC4, TIM_IC_FALLING);
  timer_ic_enable(TIM2, TIM_IC4);

  timer_enable_counter(TIM2);
  timer_enable_irq(TIM2, TIM_DIER_CC2IE);
  timer_enable_irq(TIM2, TIM_DIER_CC3IE);
  timer_enable_irq(TIM2, TIM_DIER_CC4IE);
  nvic_enable_irq(NVIC_TIM2_IRQ);
  nvic_set_priority(NVIC_TIM2_IRQ, 0);
}
示例#13
0
static WRITE8_HANDLER(svision_w)
{
	int value;
	int delay;

	svision_reg[offset] = data;

	switch (offset)
	{
		case 2:
		case 3:
			break;
		case 0x26: /* bits 5,6 memory management for a000? */
			logerror("%.6f svision write %04x %02x\n",timer_get_time(),offset,data);
			memory_set_bankptr(1, memory_region(REGION_USER1) + ((svision_reg[0x26] & 0xe0) << 9));
			svision_irq();
			break;
		case 0x23: /* delta hero irq routine write */
			value = data;
			if (!data)
				value = 0x100;
			if (BANK & 0x10)
				delay = 16384;
			else
				delay = 256;
			timer_enable(svision.timer1, TRUE);
			timer_reset(svision.timer1, TIME_IN_CYCLES(value * delay, 0));
			break;
		case 0x10: case 0x11: case 0x12: case 0x13:
			svision_soundport_w(svision_channel + 0, offset & 3, data);
			break;
		case 0x14: case 0x15: case 0x16: case 0x17:
			svision_soundport_w(svision_channel + 1, offset & 3, data);
			break;
		case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c:
			svision_sounddma_w(offset - 0x18, data);
			break;
		case 0x28: case 0x29: case 0x2a:
			svision_noise_w(offset - 0x28, data);
			break;
		default:
			logerror("%.6f svision write %04x %02x\n", timer_get_time(), offset, data);
			break;
	}
}
示例#14
0
文件: led.c 项目: hyrant/fulcrum
void LED_init(void)
{
    rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
    
    set_led(false);
     
    timer_reset(TIM2);
    timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
    timer_set_prescaler(TIM2, 256);
    timer_enable_preload(TIM2);
    timer_one_shot_mode(TIM2);
    timer_set_period(TIM2, (uint16_t)((rcc_ppre1_frequency/256) / 20));
    timer_enable_irq(TIM2, TIM_DIER_UIE);
    timer_clear_flag(TIM2, TIM_SR_UIF);
    
    nvic_enable_irq(NVIC_TIM2_IRQ);
    nvic_set_priority(NVIC_TIM2_IRQ, 128);
}
示例#15
0
文件: mvs.c 项目: AMSMM/NJEMU
static void neogeo_reset(void)
{
	video_set_mode(16);

	video_clear_screen();

	timer_reset();
	input_reset();

	neogeo_driver_reset();
	neogeo_video_reset();

	sound_reset();
	blit_clear_all_sprite();
	autoframeskip_reset();

	Loop = LOOP_EXEC;
}
示例#16
0
文件: snake.c 项目: elleveldy/byggern
void snake_settings(){
	uint8_t difficulty;
	

	while(1){
		
		
		difficulty = slider_right_read();
		
		if(timer_read(TIMER_3) > 1000){
			
			oled_clear_screen();
			oled_put_string(0*8, 0, "Set difficulty");
			oled_put_string(0, 1, "Difficulty:%u", difficulty);
			oled_put_string(0, 3, "Walls");
			if(no_walls){
				oled_put_string(7*8,3,"OFF");
			}
			else{
				oled_put_string(7*8,3,"ON");
			}
			
			oled_write_screen();
			if(button_right_read()){
				if(no_walls){
					no_walls = 0;
				}
				else{
					no_walls = 1;
				}
			}
			
			timer_reset(TIMER_3);
		}
		
		if(button_left_read()){
			if(difficulty < 1){
				s_difficulty = 1;
			}
			s_difficulty = difficulty / 4;
			return;
		}
	}
}
示例#17
0
void baro_init()
{
    gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14);
    gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
            GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15);
    gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
            GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
    deselect_slave();

    spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL,
            SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
    spi_enable_ss_output(SPI2);
    spi_enable(SPI2);

    dma_set_peripheral_address(DMA1, DMA_CHANNEL3, SPI2_DR);
    dma_set_read_from_memory(DMA1, DMA_CHANNEL3);
    dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3);
    dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT);
    dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT);
    dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH);

    dma_set_peripheral_address(DMA1, DMA_CHANNEL4, SPI2_DR);
    dma_set_read_from_peripheral(DMA1, DMA_CHANNEL4);
    dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL4);
    dma_set_peripheral_size(DMA1, DMA_CHANNEL4, DMA_CCR_PSIZE_8BIT);
    dma_set_memory_size(DMA1, DMA_CHANNEL4, DMA_CCR_MSIZE_8BIT);
    dma_set_priority(DMA1, DMA_CHANNEL4, DMA_CCR_PL_VERY_HIGH);
    dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL4);

    timer_reset(TIM4);
    timer_enable_irq(TIM4, TIM_DIER_UIE);
    timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT,
            TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
    /* 3200 / 16 = 200 Hz */
    timer_set_prescaler(TIM4, 32);
    timer_set_period(TIM4, 5625);

    nvic_set_priority(NVIC_TIM4_IRQ, 16 * 2);
    nvic_set_priority(NVIC_DMA1_CHANNEL4_IRQ, 16 * 2);
    nvic_enable_irq(NVIC_TIM4_IRQ);
    nvic_enable_irq(NVIC_DMA1_CHANNEL4_IRQ);

    read_calibration_data();
}
示例#18
0
文件: tiling.c 项目: gwash/ion-3plus
bool tiling_managed_prepare_focus(WTiling *ws, WRegion *reg, 
                                 int flags, WPrepareFocusResult *res)
{
    WSplitRegion *node; 

    if(!region_prepare_focus((WRegion*)ws, flags, res))
        return FALSE;
    
    node=get_node_check(ws, reg);
    
    if(node!=NULL && node->split.parent!=NULL)
        splitinner_mark_current(node->split.parent, &(node->split));
        
    /* WSplitSplit uses activity based stacking as required on WAutoWS,
     * so we must restack here.
     */
    if(ws->split_tree!=NULL){
        int rd=mod_tiling_raise_delay;
        bool use_timer=rd>0 && flags&REGION_GOTO_ENTERWINDOW;
        
        if(use_timer){
            if(restack_timer!=NULL){
                Obj *obj=restack_timer->objwatch.obj;
                if(obj!=(Obj*)ws){
                    timer_reset(restack_timer);
                    restack_handler(restack_timer, obj);
                }
            }else{
                restack_timer=create_timer();
            }
        }
        
        if(use_timer && restack_timer!=NULL){
            timer_set(restack_timer, rd, restack_handler, (Obj*)ws);
        }else{
            split_restack(ws->split_tree, ws->dummywin, Above);
        }
    }

    res->reg=reg;
    res->flags=flags;
    return TRUE;
}
void timer_setup(void)
{
	rcc_periph_clock_enable(RCC_TIM2);
	nvic_enable_irq(NVIC_TIM2_IRQ);
	nvic_set_priority(NVIC_TIM2_IRQ, 1);
	timer_reset(TIM2);
/* Timer global mode: - No Divider, Alignment edge, Direction up */
	timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
		       TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
	timer_continuous_mode(TIM2);
/* Set timer prescaler. 72MHz/1440 => 50000 counts per second. */
	timer_set_prescaler(TIM2, 1440);
/* End timer value. When this is reached an interrupt is generated. */
	timer_set_period(TIM2, BLINK_INTERVAL);
/* Update interrupt enable. */
	timer_enable_irq(TIM2, TIM_DIER_UIE);
/* Start timer. */
	timer_enable_counter(TIM2);
}
示例#20
0
文件: timer.c 项目: ntrtrung/eBATMAN
// init a timer handle and return a pointer to it;
// return NULL in case of error
timer_handle *timer_init(void)
{
  timer_handle *handle;
  
  // allocte the timer handle
  if((handle = (timer_handle *)malloc(sizeof(timer_handle))) == NULL) 
    {
      WARNING("Could not allocate memory for the timer");
      return NULL;
    }

  // store CPU frequency
  handle->cpu_frequency = get_cpu_frequency();

  // reset the timer so that 'zero' has a reasonable value
  timer_reset(handle);

  return handle;
}
示例#21
0
/* Timer functions */
static timeval_t
vrrp_compute_timer(const int fd)
{
	vrrp_t *vrrp;
	element e;
	list l = &vrrp_data->vrrp_index_fd[fd%1024 + 1];
	timeval_t timer;

	/* Multiple instances on the same interface */
	timer_reset(timer);
	for (e = LIST_HEAD(l); e; ELEMENT_NEXT(e)) {
		vrrp = ELEMENT_DATA(e);
		if (timer_cmp(vrrp->sands, timer) < 0 ||
		    timer_isnull(timer))
			timer = timer_dup(vrrp->sands);
	}

	return timer;
}
static void timer_setup(void)
{
	/* Set up the timer TIM2 for injected sampling */
	uint32_t timer;

	timer   = TIM2;
	rcc_periph_clock_enable(RCC_TIM2);

	/* Time Base configuration */
    timer_reset(timer);
    timer_set_mode(timer, TIM_CR1_CKD_CK_INT,
	    TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
    timer_set_period(timer, 0xFF);
    timer_set_prescaler(timer, 0x8);
    timer_set_clock_division(timer, 0x0);
    /* Generate TRGO on every update. */
    timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE);
    timer_enable_counter(timer);
}
示例#23
0
void hbridge_init() {
  // M- bridge
  // A9 - pin 21 - PWM2A - HIN
  // B0 - pin 15 - PWM2B - \LIN
  
  // M+ bridge
  // A8 - pin 20 - PWM1A - HIN
  // A7 - pin 14 - PWM1B - \LIN
  
  rcc_peripheral_enable_clock(&RCC_APB2ENR,
    RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |
    RCC_APB2ENR_AFIOEN | RCC_APB2ENR_TIM1EN);
  
  AFIO_MAPR |= AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP;
  gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
                GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7 | GPIO8 | GPIO9);
  gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
                GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO0);
  
  timer_reset(TIM1);
  timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1,
                 TIM_CR1_DIR_UP);
  timer_set_period(TIM1, half_period_ticks);
  timer_set_prescaler(TIM1, 9); // / 10
  
  timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2);
  timer_set_oc_polarity_high(TIM1, TIM_OC1);
  timer_set_oc_polarity_low(TIM1, TIM_OC1N);
  timer_enable_oc_output(TIM1, TIM_OC1);
  timer_enable_oc_output(TIM1, TIM_OC1N);
  timer_set_oc_value(TIM1, TIM_OC1, half_period_ticks);
  
  timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM2);
  timer_set_oc_polarity_high(TIM1, TIM_OC2);
  timer_set_oc_polarity_low(TIM1, TIM_OC2N);
  timer_enable_oc_output(TIM1, TIM_OC2);
  timer_enable_oc_output(TIM1, TIM_OC2N);
  timer_set_oc_value(TIM1, TIM_OC2, half_period_ticks);
  
  timer_enable_break_main_output(TIM1);
  timer_enable_counter(TIM1);
}
示例#24
0
void task (void * arg)
{
    timer_start(tt);

    t0 = time(0);

    char c;
    for(;;)
    {
        scanf("%c", &c);
        if(c == 'r')
            timer_reset(tt);
        if(c == 's')
            timer_stop(tt);
        if(c == 'c')
             break;
    }

    printf("Koniec taska\n");
}
示例#25
0
/**
 * \fn void beep_low_ms(uint16_t ms)
 * \brief Generate 2Khz sine signal for x miliseconds.
 * \param ms Number of miliseconds.
 * */
void beep_low_ms(uint16_t ms)
{
    uint32_t count = ((uint32_t)ms*1000)/50;
    uint16_t counter = 50;
    uint32_t i;


    timer_reset();

    for(i=0; i<count; i++)
    {
        DAC_SetChannel2Data(DAC_Align_12b_R, sine_samples[sine_samples_index]);

        while(abs_diff(counter,timer_get_value())<50) {}
        counter+=50;

        sine_samples_index++;
        if(sine_samples_index==SINE_SAMPLES_COUNT) sine_samples_index = 0;
    }
}
示例#26
0
void gps_init()
{
    int ok;

    calculate_crc_and_ack(set_navmode, sizeof(set_navmode));
    cm3_assert(set_navmode[sizeof(set_navmode) - 2] == 94);
    cm3_assert(set_navmode[sizeof(set_navmode) - 1] == 235);
    cm3_assert(expect_ack[8] == 49);
    cm3_assert(expect_ack[9] == 89);

    gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
              GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO2);
    gpio_set_mode(GPIOA, GPIO_MODE_INPUT,
              GPIO_CNF_INPUT_PULL_UPDOWN, GPIO3);

    usart_set_baudrate(USART2, 9600);
    usart_set_databits(USART2, 8);
    usart_set_stopbits(USART2, USART_STOPBITS_1);
    usart_set_mode(USART2, USART_MODE_TX);
    usart_set_parity(USART2, USART_PARITY_NONE);
    usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);

    usart_enable(USART2);

    timer_reset(TIM5);
    timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT,
            TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
    /* 2Hz */
    timer_set_prescaler(TIM5, 640);
    timer_set_period(TIM5, 28125);

    ok = silence_nmea();
    if (!ok) goto bail;

    ok = command(set_port, sizeof(set_port));
    if (!ok) goto bail;

bail:
    asm("nop");
}
示例#27
0
void freq_capture_setup(void) {
	/* Configure PE11 (AF1: TIM1_CH2) (SYNC_IN). */
	rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
	gpio_mode_setup(GPIOE, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
	gpio_set_af(GPIOE, GPIO_AF1, GPIO11);

	/* Timer1: Input compare */
	/* Enable timer clock. */
	rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
	/* Reset timer. */
	timer_reset(TIM1);
	/* Configure timer1. */
	timer_set_mode(TIM1,
			TIM_CR1_CKD_CK_INT,		// Internal clock
			TIM_CR1_CMS_EDGE,			// Edge synchronization
			TIM_CR1_DIR_UP);			// Count upward
	timer_set_prescaler(TIM1, TIMER1_PRESCALER);
	timer_set_period(TIM1, TIMER1_PERIOD); //Sets TIM1_ARR
	timer_continuous_mode(TIM1);
	/* Configure PE13: Toggle pin on falling edge via interrupt */
	//rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
	//gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, GPIO13);
	/* Configure input capture. */
	timer_ic_disable(TIM1, TIM_IC2);
	timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING);
	timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF);
	timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2);
	// See RM, p. 561: digital filter
	//timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_DTF_DIV_32_N_8);
	timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF);
	timer_ic_enable(TIM1, TIM_IC2);
	/* Enable counter. */
	timer_enable_counter(TIM1);
	timer_clear_flag (TIM1, TIM_SR_CC2IF);
	/* Enable IRQs */
	nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ);
	timer_enable_irq(TIM1, TIM_DIER_UIE);
	nvic_enable_irq(NVIC_TIM1_CC_IRQ);
	timer_enable_irq(TIM1, TIM_DIER_CC2IE);
}
示例#28
0
static void platform_init_freqsensor(unsigned char pin) {
  uint32_t tim;
  switch(pin) {
    case 1:
      /* TIM1 CH1 */
      tim = TIM1;
      gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8);
      gpio_set_af(GPIOA, GPIO_AF1, GPIO8);
      break;
  };
  timer_reset(tim);
  timer_set_mode(tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
  timer_set_period(tim, 0xFFFFFFFF);
  timer_disable_preload(tim);
  timer_continuous_mode(tim);
  /* Setup output compare registers */
  timer_disable_oc_output(tim, TIM_OC1);
  timer_disable_oc_output(tim, TIM_OC2);
  timer_disable_oc_output(tim, TIM_OC3);
  timer_disable_oc_output(tim, TIM_OC4);

  /* Set up compare */
  timer_ic_set_input(tim, TIM_IC1, TIM_IC_IN_TI1);
  timer_ic_set_filter(tim, TIM_IC1, TIM_IC_CK_INT_N_8);
  timer_ic_set_polarity(tim, TIM_IC1, TIM_IC_RISING);
  timer_set_prescaler(tim, 2*SENSOR_FREQ_DIVIDER); /* Prescale set to map up to 20kHz */
  timer_slave_set_mode(tim, TIM_SMCR_SMS_RM);
  timer_slave_set_trigger(tim, TIM_SMCR_TS_IT1FP1);
  timer_ic_enable(tim, TIM_IC1);

  timer_enable_counter(tim);
  timer_enable_irq(tim, TIM_DIER_CC1IE);

  switch(pin) {
    case 1:
      nvic_enable_irq(NVIC_TIM1_CC_IRQ);
      nvic_set_priority(NVIC_TIM1_CC_IRQ, 64);
      break;
  }
}
示例#29
0
static void vc20_prg_timer (int data)
{
	if (!tape.data)
	{								   /* send the same low phase */
		if (tape.noise)
			DAC_data_w (0, 0);
		tape.data = 1;
		timer_reset (prg.timer, prg.lasttime);
	}
	else
	{
		if (tape.noise)
			DAC_data_w (0, TONE_ON_VALUE);
		tape.data = 0;
		if (prg.statebit)
		{
			vc20_tape_bit (0);
		}
		else if (prg.statebyte)
		{							   /* send the rest of the byte */
			vc20_tape_byte ();
		}
		else if (prg.stateheader)
		{
			vc20_tape_prgheader ();
		}
		else
		{
			vc20_tape_program ();
			if (!prg.stateblock)
			{
				tape.play = 0;
			}
		}
	}
	if (tape.read_callback)
		tape.read_callback (0, tape.data);
	vc20_prg_state ();
}
示例#30
0
文件: timer.c 项目: ReconOS/reconos
/*
 * @see header
 */
void timer_init() {
	int fd;

	fd = open("/dev/mem", O_RDWR | O_SYNC);
	if (fd < 0) {
		printf("ERROR: Could not open /dev/mem\n");
		close(fd);
		return;
	}

	ptr = (uint32_t *)mmap(0, 0x10000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, TIMER_BASE_ADDR);
	if (ptr == MAP_FAILED) {
		printf("ERROR: Could not map memory\n");
		close(fd);
		return;
	}

	close(fd);

	timer_reset();
	timer_setstep(0);
}