/// test few results known as good
static void test_t1(void **state)
{
(void) state; // unused
ptr_exp2 = 0;
tv_exp1.tv_sec = 0;
tv_exp1.tv_usec = 0;
tv_exp2.tv_sec = 0;
tv_exp2.tv_usec = 0;
timer_t *timer = timer_create();
assert_non_null(timer);
assert_true(timer_register(timer, callback1, (void *)1000));
tv_exp1.tv_usec = 1;
timer_tick(timer, false, 1);
timer_cancel(timer, callback1, (void *)1000);
assert_true(timer_register(timer, callback1, (void *)1000));
assert_false(timer_register(timer, callback1, (void *)1000));
assert_true(timer_register(timer, callback2, (void *)0x100));
assert_true(timer_register(timer, callback2, (void *)0x200));
timer_cancel(timer, callback1, (void *)1000);
timer_cancel(timer, callback1, (void *)1000);
tv_exp1.tv_usec = -1;
tv_exp2.tv_usec = 3;
timer_tick(timer, false, 2);
assert_int_equal(ptr_exp2, 0x300);
timer_destroy(timer);
}
static unsigned char getbyte(void) {
unsigned t0 = timer_tick();
// while uart not ready, just keep going; nak every 4 sec
while(((uart_lcr() & 0x01) == 0)) {
unsigned t = timer_tick();
if ((t - t0) >= 4000000) {
uart_send(NAK);
t0 = t;
}
}
return uart_recv();
}
static irqreturn_t gpl32900b_timer_interrupt(int irq, void *dev_id)
{
#if 0
if (TMISR_0 == 1) {
timer_tick();
TMISR_0 = 0;
return IRQ_HANDLED;
}
return IRQ_NONE;
#else
timer_tick();
TMISR_0 = 0;
return IRQ_HANDLED;
#endif
}
/*!
* IRQ handler for the timer
*/
static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
{
if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
do {
timer_tick();
/*
* this algorithm takes care of possible delay
* for this interrupt handling longer than a normal
* timer period
*/
__raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
HSTIM_MATCH0);
__raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
/*
* The goal is to keep incrementing HSTIM_MATCH0
* register until HSTIM_MATCH0 indicates time after
* what HSTIM_COUNTER indicates.
*/
} while ((signed)
(__raw_readl(HSTIM_MATCH0) -
__raw_readl(HSTIM_COUNTER)) < 0);
}
return IRQ_HANDLED;
}
static irqreturn_t
w90x900_timer_interrupt(int irq, void *dev_id)
{
timer_tick();
__raw_writel(0x01, REG_TISR); /* clear TIF0 */
return IRQ_HANDLED;
}
static irqreturn_t nk_vtick_timer_interrupt(int irq, void *dev_id)
{
unsigned long now;
now = nktick->last_stamp;
while (now - nk_vtick_last_tick >= nk_vtick_ticks_per_hz) {
#ifdef NK_VTICK_MODULO
/* Modulo addition may put nk_vtick_last_tick ahead of now
* and cause unwanted repetition of the while loop.
*/
if (unlikely(now - nk_vtick_last_tick == ~0))
break;
nk_modulo_count += nk_vtick_modulo;
if (nk_modulo_count > HZ) {
++nk_vtick_last_tick;
nk_modulo_count -= HZ;
}
#endif
nk_vtick_last_tick += nk_vtick_ticks_per_hz;
timer_tick();
}
return IRQ_HANDLED;
}
static irqreturn_t
pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
int next_match;
write_seqlock(&xtime_lock);
/* Loop until we get ahead of the free running timer.
* This ensures an exact clock tick count and time accuracy.
* IRQs are disabled inside the loop to ensure coherence between
* lost_ticks (updated in do_timer()) and the match reg value, so we
* can use do_gettimeofday() from interrupt handlers.
*
* HACK ALERT: it seems that the PXA timer regs aren't updated right
* away in all cases when a write occurs. We therefore compare with
* 8 instead of 0 in the while() condition below to avoid missing a
* match if OSCR has already reached the next OSMR value.
* Experience has shown that up to 6 ticks are needed to work around
* this problem, but let's use 8 to be conservative. Note that this
* affect things only when the timer IRQ has been delayed by nearly
* exactly one tick period which should be a pretty rare event.
*/
do {
timer_tick(regs);
OSSR = OSSR_M0; /* Clear match on timer 0 */
next_match = (OSMR0 += LATCH);
} while( (signed long)(next_match - OSCR) <= 8 );
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
unsigned int mpeg_idle(mpeg_struct_t *Mpeg_Struct, new_screen* ScreenBuff, FileInfo_t *mpgfile)
{
if(!Mpeg_Struct) return 0;
if(!Mpeg_Struct->FrameReady)
{
do
{
Mpeg_Struct->state = mpeg2_parse(Mpeg_Struct->decoder);
switch (Mpeg_Struct->state)
{
case STATE_BUFFER:
//size = fread (buffer, 1, _BUFFER_SIZE_, mpgfile);
Mpeg_Struct->size = read_from_buffer(Mpeg_Struct->buffer, 1, _BUFFER_SIZE_, mpgfile);
if(!Mpeg_Struct->size) break;
mpeg2_buffer (Mpeg_Struct->decoder, Mpeg_Struct->buffer, Mpeg_Struct->buffer + Mpeg_Struct->size);
break;
case STATE_SEQUENCE:
mpeg2_convert (Mpeg_Struct->decoder, Mpeg_Struct->mpeg_convert, NULL);
break;
case STATE_SLICE:
case STATE_END:
case STATE_INVALID_END:
if (Mpeg_Struct->info->display_fbuf) Mpeg_Struct->FrameReady = 1;
break;
default:
break;
}
}while(!Mpeg_Struct->FrameReady && Mpeg_Struct->size);
}
#ifndef AVR32
if(Mpeg_Struct->FrameReady == true && (timer_tick(&Mpeg_Struct->FrameDisplay) == true || Mpeg_Struct->EnableFrameLimit == false))
#else
if(Mpeg_Struct->FrameReady == true)
#endif
{
Mpeg_Struct->FrameReady = false;
/*save_ppm (ScreenBuff, Mpeg_Struct->info->sequence->width, Mpeg_Struct->info->sequence->height,
Mpeg_Struct->info->display_fbuf->buf[0], Mpeg_Struct->framenum++);*/
_Fps++;
//Mpeg_Struct->->info
if(Mpeg_Struct->info->current_picture->temporal_reference != Mpeg_Struct->temporal_reference)
{
Mpeg_Struct->temporal_reference = Mpeg_Struct->info->current_picture->temporal_reference;
Mpeg_Struct->CallbackDisplayFrame((void*)Mpeg_Struct->CallbackDisplayFrameVariable, Mpeg_Struct->info->display_fbuf->buf[0], 0, 0, Mpeg_Struct->info->sequence->width, Mpeg_Struct->info->sequence->height);
}
if(CntToDetermineTheFps != rtcSecUpdate)
{
CntToDetermineTheFps = rtcSecUpdate;
//UARTPuts(DebugCom, "Screen fill capability = ", -1);
UARTPutNum(DebugCom, _Fps);
UARTPuts(DebugCom, "Fps\n\r", -1);
_Fps = 0;
}
}
//if(Mpeg_Struct->size == 0) mpeg2_close (Mpeg_Struct->decoder);
return Mpeg_Struct->size;
}
bool srf02_read(SRF02_t *structure) {
if(timer_tick(&structure->Timeout_Timer)) {
structure->busy = false;
return false;
}
if(!structure->busy)
return false;
Twi_t* TwiStruct = structure->TWI;
unsigned char dev_addr = 0x70;
if(structure->addr)
dev_addr = structure->addr;
unsigned char reg = 2;
unsigned char result[2];
switch(structure->reg_inst)
{
case SRF02_START_RANGING:
case SRF02_FAKE_RANGING:
if(!twi.trx(TwiStruct, dev_addr, ®, 1, result, 2))
return false;
else {
structure->range_value = result[0] << 8;
structure->range_value |= result[1];
return true;
}
break;
default:
return false;
}
return true;
}
/*
* IRQ handler for the timer
*/
static irqreturn_t
integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
write_seqlock(&xtime_lock);
/*
* clear the interrupt
*/
writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
/*
* the clock tick routines are only processed on the
* primary CPU
*/
if (hard_smp_processor_id() == 0) {
timer_tick(regs);
#ifdef CONFIG_SMP
smp_send_timer();
#endif
}
#ifdef CONFIG_SMP
/*
* this is the ARM equivalent of the APIC timer interrupt
*/
update_process_times(user_mode(regs));
#endif /* CONFIG_SMP */
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
{
__ipipe_tsc_update();
at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
timer_tick();
return IRQ_HANDLED;
}
void timer_update() {
u64 tcurr;
sceRtcGetCurrentTick(&tcurr);
int curr = (int)((tcurr-timer_t0)/10000);
while(timer_curr<curr)
timer_tick();
}
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
timer_tick();
return IRQ_HANDLED;
}
static irqreturn_t
sa1100_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned int next_match;
write_seqlock(&xtime_lock);
#ifdef CONFIG_NO_IDLE_HZ
if (match_posponed) {
match_posponed = 0;
OSMR0 = initial_match;
}
#endif
/*
* Loop until we get ahead of the free running timer.
* This ensures an exact clock tick count and time accuracy.
* Since IRQs are disabled at this point, coherence between
* lost_ticks(updated in do_timer()) and the match reg value is
* ensured, hence we can use do_gettimeofday() from interrupt
* handlers.
*/
do {
timer_tick(regs);
OSSR = OSSR_M0; /* Clear match on timer 0 */
next_match = (OSMR0 += LATCH);
} while ((signed long)(next_match - OSCR) <= 0);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
void coretimer_update(struct core_timer* timer, struct core_poller* io)
{
uint32_t diff, i;
uint64_t now_tick = gettime();
LOCK(&timer->lock);
if (now_tick < timer->timer_tick) {
diff = (uint32_t)(_UI64_MAX - timer->timer_tick + now_tick);
fprintf(stderr, "timer %p rewind from %lld to %lld\n", timer, now_tick, timer->timer_tick);
} else if (now_tick != timer->timer_tick) {
diff = (uint32_t)(now_tick - timer->timer_tick);
}
else {
diff = 0;
}
if (diff > 0) {
timer->timer_tick = now_tick;
UNLOCK(&timer->lock);
for (i = 0; i<diff; i++) {
timer_tick(timer, io);
}
} else {
UNLOCK(&timer->lock);
}
}
/*
* Timer interrupt handler
*/
static irqreturn_t
h7201_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
timer_tick(regs);
return IRQ_HANDLED;
}
void SysTick_Handler (void)
{
millis++;
timer_tick();
Tick();
if(timingDelay > 0) timingDelay--;
}
/* Although we have two interrupt lines for the timers, we only have one
* status register which clears all pending timer interrupts on reading. So
* we have to handle all timer interrupts in one place.
*/
static void
h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
if ( mask & TSTAT_T0INT ) {
timer_tick(regs);
if( mask == TSTAT_T0INT )
return;
}
mask >>= 1;
irq = IRQ_TIMER1;
desc = irq_desc + irq;
while (mask) {
if (mask & 1)
desc->handle(irq, desc, regs);
irq++;
desc++;
mask >>= 1;
}
}
DXL_COMM_ERR dxl_ping(DXL_ACTUATOR_t *settings, unsigned char id, unsigned char* err) {
char tx_buff[6];
tx_buff[0] = 0xFF;
tx_buff[1] = 0xFF;
tx_buff[2] = id;
tx_buff[3] = 2;
tx_buff[4] = DXL_PING;
tx_buff[5] = 0x0;
dxl_insert_checksum(tx_buff);
gpio.out(settings->TxEnGpio, 1);
uart.puts(settings->Uart, tx_buff, tx_buff[3] + 4);
gpio.out(settings->TxEnGpio, 0);
unsigned char rx_cnt = 0;
signed short rx_char;
char rx_buff[150];
memset(rx_buff, 0, 150);
bool preamble_ok = false;
DXL_COMM_ERR errors = DXL_COMM_RXTIMEOUT;
timer(timeout_timer);
timer_interval(&timeout_timer, settings->timeout);
while(1) {
timer_enable(&timeout_timer);
while(1) {
rx_char = uart.getc_no_blocking(settings->Uart);
if(rx_char != (signed short)-1) {
if(rx_char == 0xFF && preamble_ok == false && rx_cnt < 2) {
rx_buff[rx_cnt] = rx_char;
rx_cnt++;
break;
}
if(rx_char != 0xFF && rx_cnt == 1 && preamble_ok == false)
rx_cnt = 0;
if(rx_char != 0xFF && rx_cnt == 2 && preamble_ok == false)
preamble_ok = true;
if(preamble_ok == true) break;
}
if(timer_tick(&timeout_timer)) {
return errors;
}
}
if(preamble_ok) {
if(rx_cnt < 56) rx_buff[rx_cnt++] = rx_char;
else
errors = DXL_COMM_OVERFLOW;
if(rx_buff[LENGTH] > 54) {
errors = DXL_COMM_RXCORRUPT;
}
if(rx_cnt > 3) {
if(rx_cnt - 3 >= rx_buff[3]) {
if(dxl_verify_checksum(rx_buff)) {
*err = rx_buff[4];
return DXL_COMM_SUCCESS;
} else {
errors = DXL_COMM_CHECKSUM;
}
}
}
}
}
}
static irqreturn_t
isa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
timer_tick(regs);
return IRQ_HANDLED;
}
static irqreturn_t
lh7a40x_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
TIMER_EOI = 0;
timer_tick(regs);
return IRQ_HANDLED;
}
static irqreturn_t
isa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
write_seqlock(&xtime_lock);
timer_tick(regs);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
static irqreturn_t
shark_timer_interrupt(int irq, void *dev_id)
{
write_seqlock(&xtime_lock);
timer_tick();
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
void
SysTick_Handler (void)
{
#if defined(USE_HAL_DRIVER)
HAL_IncTick();
#endif
timer_tick ();
}
static irqreturn_t
lh7a40x_timer_interrupt(int irq, void *dev_id)
{
TIMER_EOI = 0;
timer_tick();
return IRQ_HANDLED;
}
static irqreturn_t
timer1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
*CSR_TIMER1_CLR = 0;
timer_tick(regs);
return IRQ_HANDLED;
}
/* We enter here with IRQs enabled */
static irqreturn_t
aaec2000_timer_interrupt(int irq, void *dev_id)
{
/* TODO: Check timer accuracy */
timer_tick();
TIMER1_CLEAR = 1;
return IRQ_HANDLED;
}
/*
* Clock interrupt service routine.
* No H/W reprogram is required.
*/
static int
clock_isr(int irq)
{
irq_lock();
timer_tick();
irq_unlock();
return INT_DONE;
}
/* Timing function which calls all 100ms the timer_tick from TCPnet lib -----*/
static void timer_poll () {
/* System tick timer running in poll mode */
if (SysTick->CTRL & 0x10000) {
/* Timer tick every 100 ms */
timer_tick ();
}
}
__task void timer_task (void) {
/* System tick timer task */
os_itv_set (10);
while (1) {
timer_tick ();
tick = __TRUE;
os_itv_wait ();
}
}
