static int altera_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct altera_gpio_chip *altera_gc = container_of(mm_gc, struct altera_gpio_chip, mmchip); if (altera_gc->irq == 0) return -ENXIO; if ((altera_gc->irq && offset) < altera_gc->mmchip.gc.ngpio) return irq_create_mapping(altera_gc->irq, offset); else return -ENXIO; }
static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); unsigned long flags; u32 pin_mask = 1 << (31 - gpio); spin_lock_irqsave(&cpm1_gc->lock, flags); __cpm1_gpio32_set(mm_gc, pin_mask, value); spin_unlock_irqrestore(&cpm1_gc->lock, flags); }
/** * xgpio_get - Read the specified signal of the GPIO device. * @gc: Pointer to gpio_chip device structure. * @gpio: GPIO signal number. * * This function reads the specified signal of the GPIO device. It returns 0 if * the signal clear, 1 if signal is set or negative value on error. */ static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct xgpio_instance *chip = container_of(mm_gc, struct xgpio_instance, mmchip); if ((chip->isdual) && (gpio >= chip->gpio_width)) { gpio -= chip->gpio_width; if(((chip->gpio2_dir) >> gpio) & 1) { return (in_be32(mm_gc->regs + XGPIO2_DATA_OFFSET) >> gpio) & 1; } else { return ((chip->gpio2_state >> gpio) & 1);
static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); unsigned long flags; spin_lock_irqsave(&mpc8xxx_gc->lock, flags); clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); return 0; }
static int gef_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int value) { unsigned int data; struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip); /* Set value before switching to output */ gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value); data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT); data = data & ~BIT(offset); iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT); return 0; }
static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct altera_gpio_chip *chip = container_of(mm_gc, struct altera_gpio_chip, mmchip); unsigned long flags; unsigned int data_reg; spin_lock_irqsave(&chip->gpio_lock, flags); data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); data_reg = (data_reg & ~(1 << offset)) | (value << offset); writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA); spin_unlock_irqrestore(&chip->gpio_lock, flags); }
/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs * defined as output cannot be determined by reading GPDAT register, * so we use shadow data register instead. The status of input pins * is determined by reading GPDAT register. */ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) { u32 val; struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); u32 out_mask, out_shadow; out_mask = in_be32(mm->regs + GPIO_DIR); val = in_be32(mm->regs + GPIO_DAT) & ~out_mask; out_shadow = mpc8xxx_gc->data & out_mask; return (val | out_shadow) & mpc8xxx_gpio2mask(gpio); }
static int milkymist_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, int value) { struct of_mm_gpio_chip *mm_chip = to_of_mm_gpio_chip(gc); struct milkymist_gpio_chip *chip = container_of(mm_chip, struct milkymist_gpio_chip, mm_gc); if (gpio < chip->num_gpi) return -EINVAL; milkymist_gpio_set(gc, gpio, value); return 0; }
static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); struct cpm_ioport32b __iomem *iop = mm_gc->regs; unsigned long flags; u32 pin_mask = 1 << (31 - gpio); spin_lock_irqsave(&cpm1_gc->lock, flags); clrbits32(&iop->dir, pin_mask); spin_unlock_irqrestore(&cpm1_gc->lock, flags); return 0; }
static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); unsigned long flags; spin_lock_irqsave(&mpc8xxx_gc->lock, flags); if (val) mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); else mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); }
static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct altera_gpio_chip *chip = container_of(mm_gc, struct altera_gpio_chip, mmchip); unsigned long flags; unsigned int gpio_ddr; spin_lock_irqsave(&chip->gpio_lock, flags); /* Set pin as input, assumes software controlled IP */ gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); gpio_ddr &= ~(1 << offset); writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR); spin_unlock_irqrestore(&chip->gpio_lock, flags); return 0; }
static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); struct cpm_ioport16 __iomem *iop = mm_gc->regs; unsigned long flags; u16 pin_mask = 1 << (15 - gpio); spin_lock_irqsave(&cpm1_gc->lock, flags); setbits16(&iop->dir, pin_mask); __cpm1_gpio16_set(mm_gc, pin_mask, val); spin_unlock_irqrestore(&cpm1_gc->lock, flags); return 0; }
/** * xgpio_dir_in - Set the direction of the specified GPIO signal as input. * @gc: Pointer to gpio_chip device structure. * @gpio: GPIO signal number. * * Return: * 0 - if direction of GPIO signals is set as input * otherwise it returns negative error value. */ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { unsigned long flags; struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct xgpio_instance *chip = gpiochip_get_data(gc); int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); spin_lock_irqsave(&chip->gpio_lock[index], flags); /* Set the GPIO bit in shadow register and set direction as input */ chip->gpio_dir[index] |= BIT(offset); xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); spin_unlock_irqrestore(&chip->gpio_lock[index], flags); return 0; }
/** * xgpio_set - Write the specified signal of the GPIO device. * @gc: Pointer to gpio_chip device structure. * @gpio: GPIO signal number. * @val: Value to be written to specified signal. * * This function writes the specified value in to the specified signal of the * GPIO device. */ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { unsigned long flags; struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct xgpio_instance *chip = gpiochip_get_data(gc); int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); spin_lock_irqsave(&chip->gpio_lock[index], flags); /* Write to GPIO signal and set its direction to output */ if (val) chip->gpio_state[index] |= BIT(offset); else chip->gpio_state[index] &= ~BIT(offset); xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_state[index]); spin_unlock_irqrestore(&chip->gpio_lock[index], flags); }
static void milkymist_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value) { struct of_mm_gpio_chip *mm_chip = to_of_mm_gpio_chip(gc); struct milkymist_gpio_chip *chip = container_of(mm_chip, struct milkymist_gpio_chip, mm_gc); uint32_t mask; uint32_t reg; gpio -= chip->num_gpi; mask = BIT(gpio); reg = ioread32be(mm_chip->regs + GPIO_OUT); if (value) reg |= mask; else reg &= ~mask; iowrite32be(reg, mm_chip->regs + GPIO_OUT); }
static int altera_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int value) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct altera_gpio_chip *chip = container_of(mm_gc, struct altera_gpio_chip, mmchip); unsigned long flags; unsigned int data_reg, gpio_ddr; spin_lock_irqsave(&chip->gpio_lock, flags); /* Sets the GPIO value */ data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); data_reg = (data_reg & ~(1 << offset)) | (value << offset); writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA); /* Set pin as output, assumes software controlled IP */ gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); gpio_ddr |= (1 << offset); writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR); spin_unlock_irqrestore(&chip->gpio_lock, flags); return 0; }
/** * xgpio_set_multiple - Write the specified signals of the GPIO device. * @gc: Pointer to gpio_chip device structure. * @mask: Mask of the GPIOS to modify. * @bits: Value to be wrote on each GPIO * * This function writes the specified values into the specified signals of the * GPIO devices. */ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { unsigned long flags; struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); struct xgpio_instance *chip = gpiochip_get_data(gc); int index = xgpio_index(chip, 0); int offset, i; spin_lock_irqsave(&chip->gpio_lock[index], flags); /* Write to GPIO signals */ for (i = 0; i < gc->ngpio; i++) { if (*mask == 0) break; if (index != xgpio_index(chip, i)) { xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + xgpio_regoffset(chip, i), chip->gpio_state[index]); spin_unlock_irqrestore(&chip->gpio_lock[index], flags); index = xgpio_index(chip, i); spin_lock_irqsave(&chip->gpio_lock[index], flags); } if (__test_and_clear_bit(i, mask)) { offset = xgpio_offset(chip, i); if (test_bit(i, bits)) chip->gpio_state[index] |= BIT(offset); else chip->gpio_state[index] &= ~BIT(offset); } } xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + xgpio_regoffset(chip, i), chip->gpio_state[index]); spin_unlock_irqrestore(&chip->gpio_lock[index], flags); }
static int gef_gpio_get(struct gpio_chip *chip, unsigned offset) { struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip); return !!(ioread32be(mmchip->regs + GEF_GPIO_IN) & BIT(offset)); }
static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); }
static int altera_gpio_get(struct gpio_chip *gc, unsigned offset) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); return (readl(mm_gc->regs + ALTERA_GPIO_DATA) >> offset) & 1; }