int radeon_dp_get_panel_mode(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_connector *radeon_connector = to_radeon_connector(connector); int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); u8 tmp; if (!ASIC_IS_DCE4(rdev)) return panel_mode; if (dp_bridge != ENCODER_OBJECT_ID_NONE) { /* DP bridge chips */ tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); if (tmp & 1) panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; else panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { /* eDP */ tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); if (tmp & 1) panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; } return panel_mode; }
static void radeon_dp_set_panel_mode(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_connector *radeon_connector = to_radeon_connector(connector); int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; if (!ASIC_IS_DCE4(rdev)) return; if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == ENCODER_OBJECT_ID_NUTMEG) panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == ENCODER_OBJECT_ID_TRAVIS) panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); if (tmp & 1) panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; } atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP_PANEL_MODE, panel_mode); if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) && (panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { radeon_write_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_SET, 1); } }
void evergreen_enable_dp_audio_packets(struct drm_encoder *encoder, bool enable) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; uint32_t offset; if (!dig || !dig->afmt) return; offset = dig->afmt->offset; if (enable) { struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); struct radeon_connector *radeon_connector = to_radeon_connector(connector); struct radeon_connector_atom_dig *dig_connector; uint32_t val; if (dig->afmt->enabled) return; WREG32(EVERGREEN_DP_SEC_TIMESTAMP + offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); if (radeon_connector->con_priv) { dig_connector = radeon_connector->con_priv; val = RREG32(EVERGREEN_DP_SEC_AUD_N + offset); val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); if (dig_connector->dp_clock == 162000) val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); else val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); WREG32(EVERGREEN_DP_SEC_AUD_N + offset, val); } WREG32(EVERGREEN_DP_SEC_CNTL + offset, EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ radeon_audio_enable(rdev, dig->afmt->pin, 0xf); } else { if (!dig->afmt->enabled) return; WREG32(EVERGREEN_DP_SEC_CNTL + offset, 0); radeon_audio_enable(rdev, dig->afmt->pin, 0); } dig->afmt->enabled = enable; }
void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); if (!dig || !dig->afmt) return; if (enable && drm_detect_monitor_audio(radeon_connector_edid(connector))) { struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); struct radeon_connector *radeon_connector = to_radeon_connector(connector); struct radeon_connector_atom_dig *dig_connector; uint32_t val; WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, AFMT_AUDIO_SAMPLE_SEND); WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { dig_connector = radeon_connector->con_priv; val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); if (dig_connector->dp_clock == 162000) val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); else val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); } WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ } else { WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, ~AFMT_AUDIO_SAMPLE_SEND); } dig->afmt->enabled = enable; }
void radeon_dp_set_link_config(struct drm_connector *connector, const struct drm_display_mode *mode) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); struct radeon_connector_atom_dig *dig_connector; if (!radeon_connector->con_priv) return; dig_connector = radeon_connector->con_priv; if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { dig_connector->dp_clock = radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); dig_connector->dp_lane_count = radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); } }
void radeon_dp_set_rx_power_state(struct drm_connector *connector, u8 power_state) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); struct radeon_connector_atom_dig *dig_connector; if (!radeon_connector->con_priv) return; dig_connector = radeon_connector->con_priv; /* power up/down the sink */ if (dig_connector->dpcd[0] >= 0x11) { drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, DP_SET_POWER, power_state); usleep_range(1000, 2000); } }
int radeon_dp_mode_valid_helper(struct drm_connector *connector, struct drm_display_mode *mode) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); struct radeon_connector_atom_dig *dig_connector; int dp_clock; if (!radeon_connector->con_priv) return MODE_CLOCK_HIGH; dig_connector = radeon_connector->con_priv; dp_clock = radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); if ((dp_clock == 540000) && (!radeon_connector_is_dp12_capable(connector))) return MODE_CLOCK_HIGH; return MODE_OK; }
void radeon_dp_set_link_config(struct drm_connector *connector, struct drm_display_mode *mode) { struct radeon_connector *radeon_connector; struct radeon_connector_atom_dig *dig_connector; if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) && (connector->connector_type != DRM_MODE_CONNECTOR_eDP)) return; radeon_connector = to_radeon_connector(connector); if (!radeon_connector->con_priv) return; dig_connector = radeon_connector->con_priv; dig_connector->dp_clock = dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock); dig_connector->dp_lane_count = dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock); }
int radeon_dp_get_panel_mode(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_connector *radeon_connector = to_radeon_connector(connector); int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; if (!ASIC_IS_DCE4(rdev)) return panel_mode; if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == ENCODER_OBJECT_ID_NUTMEG) panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == ENCODER_OBJECT_ID_TRAVIS) { u8 id[6]; int i; for (i = 0; i < 6; i++) id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i); if (id[0] == 0x73 && id[1] == 0x69 && id[2] == 0x76 && id[3] == 0x61 && id[4] == 0x72 && id[5] == 0x54) panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; else panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); if (tmp & 1) panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; } return panel_mode; }
void radeon_dp_link_train(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder_atom_dig *dig; struct radeon_connector *radeon_connector; struct radeon_connector_atom_dig *dig_connector; struct radeon_dp_link_train_info dp_info; int index; u8 tmp, frev, crev; if (!radeon_encoder->enc_priv) return; dig = radeon_encoder->enc_priv; radeon_connector = to_radeon_connector(connector); if (!radeon_connector->con_priv) return; dig_connector = radeon_connector->con_priv; if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) return; /* DPEncoderService newer than 1.1 can't program properly the * training pattern. When facing such version use the * DIGXEncoderControl (X== 1 | 2) */ dp_info.use_dpencoder = true; index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { if (crev > 1) { dp_info.use_dpencoder = false; } } dp_info.enc_id = 0; if (dig->dig_encoder) dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; else dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; if (dig->linkb) dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; else dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) dp_info.tp3_supported = true; else dp_info.tp3_supported = false; memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); dp_info.rdev = rdev; dp_info.encoder = encoder; dp_info.connector = connector; dp_info.radeon_connector = radeon_connector; dp_info.dp_lane_count = dig_connector->dp_lane_count; dp_info.dp_clock = dig_connector->dp_clock; if (radeon_dp_link_train_init(&dp_info)) goto done; if (radeon_dp_link_train_cr(&dp_info)) goto done; if (radeon_dp_link_train_ce(&dp_info)) goto done; done: if (radeon_dp_link_train_finish(&dp_info)) return; }
void dp_link_train(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder_atom_dig *dig; struct radeon_connector *radeon_connector; struct radeon_connector_atom_dig *dig_connector; int enc_id = 0; bool clock_recovery, channel_eq; u8 link_status[DP_LINK_STATUS_SIZE]; u8 link_configuration[DP_LINK_CONFIGURATION_SIZE]; u8 tries, voltage; u8 train_set[4]; int i; if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) && (connector->connector_type != DRM_MODE_CONNECTOR_eDP)) return; if (!radeon_encoder->enc_priv) return; dig = radeon_encoder->enc_priv; radeon_connector = to_radeon_connector(connector); if (!radeon_connector->con_priv) return; dig_connector = radeon_connector->con_priv; if (dig->dig_encoder) enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; else enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; if (dig_connector->linkb) enc_id |= ATOM_DP_CONFIG_LINK_B; else enc_id |= ATOM_DP_CONFIG_LINK_A; memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); if (dig_connector->dp_clock == 270000) link_configuration[0] = DP_LINK_BW_2_7; else link_configuration[0] = DP_LINK_BW_1_62; link_configuration[1] = dig_connector->dp_lane_count; if (dig_connector->dpcd[0] >= 0x11) link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; /* power up the sink */ dp_set_power(radeon_connector, DP_SET_POWER_D0); /* disable the training pattern on the sink */ dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); /* set link bw and lanes on the sink */ dp_set_link_bw_lanes(radeon_connector, link_configuration); /* disable downspread on the sink */ dp_set_downspread(radeon_connector, 0); /* start training on the source */ radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START, dig_connector->dp_clock, enc_id, 0); /* set training pattern 1 on the source */ radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, dig_connector->dp_clock, enc_id, 0); /* set initial vs/emph */ memset(train_set, 0, 4); udelay(400); /* set training pattern 1 on the sink */ dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1); dp_update_dpvs_emph(radeon_connector, encoder, train_set); /* clock recovery loop */ clock_recovery = false; tries = 0; voltage = 0xff; for (;;) { udelay(100); if (!atom_dp_get_link_status(radeon_connector, link_status)) break; if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) { clock_recovery = true; break; } for (i = 0; i < dig_connector->dp_lane_count; i++) { if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) break; } if (i == dig_connector->dp_lane_count) { DRM_ERROR("clock recovery reached max voltage\n"); break; } if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { ++tries; if (tries == 5) { DRM_ERROR("clock recovery tried 5 times\n"); break; } } else tries = 0; voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; /* Compute new train_set as requested by sink */ dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); dp_update_dpvs_emph(radeon_connector, encoder, train_set); } if (!clock_recovery) DRM_ERROR("clock recovery failed\n"); else DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n", train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT); /* set training pattern 2 on the sink */ dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2); /* set training pattern 2 on the source */ radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, dig_connector->dp_clock, enc_id, 1); /* channel equalization loop */ tries = 0; channel_eq = false; for (;;) { udelay(400); if (!atom_dp_get_link_status(radeon_connector, link_status)) break; if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) { channel_eq = true; break; } /* Try 5 times */ if (tries > 5) { DRM_ERROR("channel eq failed: 5 tries\n"); break; } /* Compute new train_set as requested by sink */ dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set); dp_update_dpvs_emph(radeon_connector, encoder, train_set); tries++; } if (!channel_eq) DRM_ERROR("channel eq failed\n"); else DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n", train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT); /* disable the training pattern on the sink */ dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, dig_connector->dp_clock, enc_id, 0); }