static int tscadc_resume(struct device *dev) { struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev); unsigned int restore, ctrl; pm_runtime_get_sync(dev); /* context restore */ ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_TSCENB | CNTRLREG_STEPID | CNTRLREG_4WIRE; tscadc_writel(tscadc_dev, REG_CTRL, ctrl); tscadc_idle_config(tscadc_dev); tscadc_writel(tscadc_dev, REG_SE, STPENB_STEPENB); restore = tscadc_readl(tscadc_dev, REG_CTRL); tscadc_writel(tscadc_dev, REG_CTRL, (restore | CNTRLREG_TSCSSENB)); return 0; }
static int tscadc_resume(struct platform_device *pdev) { struct ti_tscadc_dev *tscadc_dev = platform_get_drvdata(pdev); struct mfd_tscadc_board *pdata = pdev->dev.platform_data; unsigned int irq_read; pm_runtime_get_sync(&pdev->dev); /* context restore */ irq_read = tscadc_readl(tscadc_dev, TSCADC_REG_IRQSTATUS); tscadc_writel(tscadc_dev, TSCADC_REG_IRQSTATUS, irq_read); tscadc_writel(tscadc_dev, TSCADC_REG_IRQENABLE, tscadc_dev->irqstat); if (pdata->tsc_init) tscadc_idle_config(tscadc_dev); tscadc_writel(tscadc_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TC); tscadc_writel(tscadc_dev, TSCADC_REG_CTRL, tscadc_dev->ctrl); return 0; }
static int __devinit ti_tscadc_probe(struct platform_device *pdev) { struct ti_tscadc_dev *tscadc; struct resource *res; struct clk *clk; struct mfd_tscadc_board *pdata = pdev->dev.platform_data; struct mfd_cell *cell; int irq; int err, ctrl; int clk_value, clock_rate; int tsc_wires = 0, adc_channels = 0, total_channels; if (!pdata) { dev_err(&pdev->dev, "Could not find platform data\n"); return -EINVAL; } if (pdata->adc_init) adc_channels = pdata->adc_init->adc_channels; if (pdata->tsc_init) tsc_wires = pdata->tsc_init->wires; total_channels = tsc_wires + adc_channels; if (total_channels > 8) { dev_err(&pdev->dev, "Number of i/p channels more than 8\n"); return -EINVAL; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "no memory resource defined.\n"); return -EINVAL; } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq ID is specified.\n"); return -EINVAL; } /* Allocate memory for device */ tscadc = devm_kzalloc(&pdev->dev, sizeof(struct ti_tscadc_dev), GFP_KERNEL); if (!tscadc) { dev_err(&pdev->dev, "failed to allocate memory.\n"); return -ENOMEM; } tscadc->dev = &pdev->dev; tscadc->irq = irq; res = devm_request_mem_region(&pdev->dev, res->start, resource_size(res), pdev->name); if (!res) { dev_err(&pdev->dev, "failed to reserve registers.\n"); err = -EBUSY; goto err; } tscadc->tscadc_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (!tscadc->tscadc_base) { dev_err(&pdev->dev, "failed to map registers.\n"); err = -ENOMEM; goto err; } tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev, tscadc->tscadc_base, &tscadc_regmap_config); if (IS_ERR(tscadc->regmap_tscadc)) { dev_err(&pdev->dev, "regmap init failed\n"); err = PTR_ERR(tscadc->regmap_tscadc); goto err; } pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); /* * The TSC_ADC_Subsystem has 2 clock domains * OCP_CLK and ADC_CLK. * The ADC clock is expected to run at target of 3MHz, * and expected to capture 12-bit data at a rate of 200 KSPS. * The TSC_ADC_SS controller design assumes the OCP clock is * at least 6x faster than the ADC clock. */ clk = clk_get(&pdev->dev, "adc_tsc_fck"); if (IS_ERR(clk)) { dev_err(&pdev->dev, "failed to get TSC fck\n"); err = PTR_ERR(clk); goto err_disable_clk; } clock_rate = clk_get_rate(clk); clk_put(clk); clk_value = clock_rate / ADC_CLK; if (clk_value < MAX_CLK_DIV) { dev_err(&pdev->dev, "clock input less than min clock requirement\n"); err = -EINVAL; goto err_disable_clk; } /* TSCADC_CLKDIV needs to be configured to the value minus 1 */ clk_value = clk_value - 1; tscadc_writel(tscadc, REG_CLKDIV, clk_value); /* Set the control register bits */ ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_TSCENB | CNTRLREG_STEPID | CNTRLREG_4WIRE; tscadc_writel(tscadc, REG_CTRL, ctrl); /* Set register bits for Idle Config Mode */ tscadc_idle_config(tscadc); /* Enable the TSC module enable bit */ ctrl = tscadc_readl(tscadc, REG_CTRL); ctrl |= CNTRLREG_TSCSSENB; tscadc_writel(tscadc, REG_CTRL, ctrl); tscadc->used_cells = 0; tscadc->tsc_cell = -1; tscadc->adc_cell = -1; /* TSC Cell */ if (tsc_wires > 0) { tscadc->tsc_cell = tscadc->used_cells; cell = &tscadc->cells[tscadc->used_cells++]; cell->name = "tsc"; cell->platform_data = tscadc; cell->pdata_size = sizeof(*tscadc); } /* ADC Cell */ if (adc_channels > 0) { tscadc->adc_cell = tscadc->used_cells; cell = &tscadc->cells[tscadc->used_cells++]; cell->name = "tiadc"; cell->platform_data = tscadc; cell->pdata_size = sizeof(*tscadc); } err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells, tscadc->used_cells, NULL, 0, NULL); if (err < 0) goto err_disable_clk; device_init_wakeup(&pdev->dev, true); platform_set_drvdata(pdev, tscadc); dev_info(&pdev->dev, "Initialized OK.\n"); return 0; err_disable_clk: pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); err: return err; }