static void fs_lower_opcode_derivative(struct toy_compiler *tc, struct toy_inst *inst) { struct toy_dst dst[4]; struct toy_src src[4]; int i; tdst_transpose(inst->dst, dst); tsrc_transpose(inst->src[0], src); /* * Every four fragments are from a 2x2 subspan, with * * fragment 1 on the top-left, * fragment 2 on the top-right, * fragment 3 on the bottom-left, * fragment 4 on the bottom-right. * * DDX should thus produce * * dst = src.yyww - src.xxzz * * and DDY should produce * * dst = src.zzww - src.xxyy * * But since we are in BRW_ALIGN_1, swizzling does not work and we have to * play with the region parameters. */ if (inst->opcode == TOY_OPCODE_DDX) { for (i = 0; i < 4; i++) { struct toy_src left, right; left = tsrc_rect(src[i], TOY_RECT_220); right = tsrc_offset(left, 0, 1); tc_ADD(tc, dst[i], right, tsrc_negate(left)); } } else { for (i = 0; i < 4; i++) { struct toy_src top, bottom; /* approximate with dst = src.zzzz - src.xxxx */ top = tsrc_rect(src[i], TOY_RECT_440); bottom = tsrc_offset(top, 0, 2); tc_ADD(tc, dst[i], bottom, tsrc_negate(top)); } } tc_discard_inst(tc, inst); }
static void gs_COPY1(struct toy_compiler *tc, struct toy_dst dst, int dst_ch, struct toy_src src, int src_ch) { struct toy_inst *inst; inst = tc_MOV(tc, tdst_offset(dst, 0, dst_ch), tsrc_rect(tsrc_offset(src, 0, src_ch), TOY_RECT_010)); inst->exec_size = GEN6_EXECSIZE_1; inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; }
static void fs_lower_opcode_tgsi_const_gen6(struct fs_compile_context *fcc, struct toy_dst dst, int dim, struct toy_src idx) { const struct toy_dst header = tdst_ud(tdst(TOY_FILE_MRF, fcc->first_free_mrf, 0)); const struct toy_dst global_offset = tdst_ud(tdst(TOY_FILE_MRF, fcc->first_free_mrf, 2 * 4)); const struct toy_src r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0)); struct toy_compiler *tc = &fcc->tc; unsigned msg_type, msg_ctrl, msg_len; struct toy_inst *inst; struct toy_src desc; struct toy_dst tmp, real_dst[4]; int i; /* set message header */ inst = tc_MOV(tc, header, r0); inst->mask_ctrl = BRW_MASK_DISABLE; /* set global offset */ inst = tc_MOV(tc, global_offset, idx); inst->mask_ctrl = BRW_MASK_DISABLE; inst->exec_size = BRW_EXECUTE_1; inst->src[0].rect = TOY_RECT_010; msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ; msg_ctrl = BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW << 8; msg_len = 1; desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false, msg_type, msg_ctrl, ILO_WM_CONST_SURFACE(dim)); tmp = tc_alloc_tmp(tc); tc_SEND(tc, tmp, tsrc_from(header), desc, fcc->const_cache); tdst_transpose(dst, real_dst); for (i = 0; i < 4; i++) { const struct toy_src src = tsrc_offset(tsrc_rect(tsrc_from(tmp), TOY_RECT_010), 0, i); /* cast to type D to make sure these are raw moves */ tc_MOV(tc, tdst_d(real_dst[i]), tsrc_d(src)); } }
static void fs_lower_opcode_tgsi_const_gen7(struct fs_compile_context *fcc, struct toy_dst dst, int dim, struct toy_src idx) { struct toy_compiler *tc = &fcc->tc; const struct toy_dst offset = tdst_ud(tdst(TOY_FILE_MRF, fcc->first_free_mrf, 0)); struct toy_src desc; struct toy_inst *inst; struct toy_dst tmp, real_dst[4]; int i; /* * In 4c1fdae0a01b3f92ec03b61aac1d3df500d51fc6, pull constant load was * changed from OWord Block Read to ld to increase performance in the * classic driver. Since we use the constant cache instead of the data * cache, I wonder if we still want to follow the classic driver. */ /* set offset */ inst = tc_MOV(tc, offset, tsrc_rect(idx, TOY_RECT_010)); inst->exec_size = BRW_EXECUTE_8; inst->mask_ctrl = BRW_MASK_DISABLE; desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false, BRW_SAMPLER_SIMD_MODE_SIMD4X2, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, 0, ILO_WM_CONST_SURFACE(dim)); tmp = tc_alloc_tmp(tc); inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, BRW_SFID_SAMPLER); inst->exec_size = BRW_EXECUTE_8; inst->mask_ctrl = BRW_MASK_DISABLE; tdst_transpose(dst, real_dst); for (i = 0; i < 4; i++) { const struct toy_src src = tsrc_offset(tsrc_rect(tsrc_from(tmp), TOY_RECT_010), 0, i); /* cast to type D to make sure these are raw moves */ tc_MOV(tc, tdst_d(real_dst[i]), tsrc_d(src)); } }
static bool gs_compile_passthrough(struct gs_compile_context *gcc) { struct toy_compiler *tc = &gcc->tc; struct ilo_shader *sh = gcc->shader; gcc->is_static = true; gcc->static_data.total_vertices = gcc->in_vue_count; gcc->static_data.total_prims = 1; gcc->static_data.last_vertex[0] = 1 << (gcc->in_vue_count - 1); gs_init_vars(gcc); gs_ff_sync(gcc, tdst_d(gcc->vars.tmp), tsrc_imm_d(gcc->static_data.total_prims)); gs_COPY1(tc, gcc->vars.urb_write_header, 0, tsrc_from(tdst_d(gcc->vars.tmp)), 0); if (gcc->write_so) gs_COPY4(tc, gcc->vars.so_index, 0, tsrc_from(tdst_d(gcc->vars.tmp)), 1); { int vert, attr; for (vert = 0; vert < gcc->out_vue_min_count; vert++) { for (attr = 0; attr < gcc->shader->out.count; attr++) { tc_MOV(tc, tdst_from(gcc->vars.tgsi_outs[attr]), tsrc_offset(gcc->payload.vues[vert], attr / 2, (attr % 2) * 4)); } gs_lower_opcode_emit(gcc, NULL); } gs_lower_opcode_endprim(gcc, NULL); } if (!gcc->write_vue) gs_discard(gcc); gs_lower_virtual_opcodes(gcc); toy_compiler_legalize_for_ra(tc); toy_compiler_optimize(tc); toy_compiler_allocate_registers(tc, gcc->first_free_grf, gcc->last_free_grf, 1); toy_compiler_legalize_for_asm(tc); if (tc->fail) { ilo_err("failed to translate GS TGSI tokens: %s\n", tc->reason); return false; } if (ilo_debug & ILO_DEBUG_GS) { int i; ilo_printf("VUE count %d, VUE size %d\n", gcc->in_vue_count, gcc->in_vue_size); ilo_printf("%srasterizer discard\n", (gcc->variant->u.gs.rasterizer_discard) ? "" : "no "); for (i = 0; i < gcc->so_info->num_outputs; i++) { ilo_printf("SO[%d] = OUT[%d]\n", i, gcc->so_info->output[i].register_index); } ilo_printf("legalized instructions:\n"); toy_compiler_dump(tc); ilo_printf("\n"); } sh->kernel = toy_compiler_assemble(tc, &sh->kernel_size); if (!sh->kernel) { ilo_err("failed to compile GS: %s\n", tc->reason); return false; } if (ilo_debug & ILO_DEBUG_GS) { ilo_printf("disassembly:\n"); toy_compiler_disassemble(tc->dev, sh->kernel, sh->kernel_size, false); ilo_printf("\n"); } return true; }
static void gs_lower_opcode_tgsi_in(struct gs_compile_context *gcc, struct toy_dst dst, int dim, int idx) { struct toy_compiler *tc = &gcc->tc; struct toy_src attr; int slot, reg = -1, subreg; slot = toy_tgsi_find_input(&gcc->tgsi, idx); if (slot >= 0) { int i; for (i = 0; i < gcc->variant->u.gs.num_inputs; i++) { if (gcc->variant->u.gs.semantic_names[i] == gcc->tgsi.inputs[slot].semantic_name && gcc->variant->u.gs.semantic_indices[i] == gcc->tgsi.inputs[slot].semantic_index) { reg = i / 2; subreg = (i % 2) * 4; break; } } } if (reg < 0) { tc_MOV(tc, dst, tsrc_imm_f(0.0f)); return; } /* fix vertex ordering for GEN6_3DPRIM_TRISTRIP_REVERSE */ if (gcc->in_vue_count == 3 && dim < 2) { struct toy_inst *inst; /* get PrimType */ inst = tc_AND(tc, tdst_d(gcc->vars.tmp), tsrc_offset(gcc->payload.header, 0, 2), tsrc_imm_d(0x1f)); inst->exec_size = GEN6_EXECSIZE_1; inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010); inst->src[1] = tsrc_rect(inst->src[1], TOY_RECT_010); inst = tc_CMP(tc, tdst_null(), tsrc_from(tdst_d(gcc->vars.tmp)), tsrc_imm_d(GEN6_3DPRIM_TRISTRIP_REVERSE), GEN6_COND_NZ); inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010); attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg); inst = tc_MOV(tc, dst, attr); inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; /* swap IN[0] and IN[1] for GEN6_3DPRIM_TRISTRIP_REVERSE */ dim = !dim; attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg); inst = tc_MOV(tc, dst, attr); inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; inst->pred_inv = true; } else { attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg); tc_MOV(tc, dst, attr); } }
static void gs_lower_opcode_emit_so_static(struct gs_compile_context *gcc) { struct toy_compiler *tc = &gcc->tc; struct toy_inst *inst; int i, j; if (gcc->static_data.num_vertices_in_prim < gcc->out_vue_min_count) return; inst = tc_MOV(tc, tdst_w(gcc->vars.tmp), tsrc_imm_v(0x03020100)); inst->exec_size = GEN6_EXECSIZE_8; inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; tc_ADD(tc, tdst_d(gcc->vars.tmp), tsrc_from(tdst_d(gcc->vars.tmp)), tsrc_rect(tsrc_from(gcc->vars.so_index), TOY_RECT_010)); tc_IF(tc, tdst_null(), tsrc_rect(tsrc_offset(tsrc_from(tdst_d(gcc->vars.tmp)), 0, gcc->out_vue_min_count - 1), TOY_RECT_010), tsrc_rect(tsrc_offset(gcc->payload.svbi, 0, 4), TOY_RECT_010), GEN6_COND_LE); { for (i = 0; i < gcc->out_vue_min_count; i++) { for (j = 0; j < gcc->so_info->num_outputs; j++) { const int idx = gcc->so_info->output[j].register_index; struct toy_src index, out; int binding_table_index; bool write_commit; index = tsrc_d(tsrc_offset(tsrc_from(gcc->vars.tmp), 0, i)); if (i == gcc->out_vue_min_count - 1) { out = gcc->vars.tgsi_outs[idx]; } else { /* gcc->vars.buffer_cur also points to the first vertex */ const int buf = (gcc->vars.buffer_cur + i) % gcc->vars.buffer_needed; out = tsrc_offset(tsrc_from(gcc->vars.buffers[buf]), idx, 0); } out = tsrc_offset(out, 0, gcc->so_info->output[j].start_component); /* * From the Sandy Bridge PRM, volume 4 part 2, page 19: * * "The Kernel must do a write commit on the last write to DAP * prior to a URB_WRITE with End of Thread." */ write_commit = (gcc->static_data.num_vertices == gcc->static_data.total_vertices && i == gcc->out_vue_min_count - 1 && j == gcc->so_info->num_outputs - 1); binding_table_index = gcc->shader->bt.gen6_so_base + j; gs_write_so(gcc, gcc->vars.tmp, index, out, write_commit, binding_table_index); /* * From the Sandy Bridge PRM, volume 4 part 1, page 168: * * "The write commit does not modify the destination register, but * merely clears the dependency associated with the destination * register. Thus, a simple "mov" instruction using the register as a * source is sufficient to wait for the write commit to occur." */ if (write_commit) tc_MOV(tc, gcc->vars.tmp, tsrc_from(gcc->vars.tmp)); } } /* SONumPrimsWritten occupies the higher word of m0.2 of URB_WRITE */ tc_ADD(tc, gcc->vars.so_written, tsrc_from(gcc->vars.so_written), tsrc_imm_d(1 << 16)); tc_ADD(tc, gcc->vars.so_index, tsrc_from(gcc->vars.so_index), tsrc_imm_d(gcc->out_vue_min_count)); } tc_ENDIF(tc); }
/** * Emit instructions to write the VUE. */ static void vs_write_vue(struct vs_compile_context *vcc) { struct toy_compiler *tc = &vcc->tc; struct toy_src outs[PIPE_MAX_SHADER_OUTPUTS]; struct toy_dst header; struct toy_src r0; struct toy_inst *inst; int sent_attrs, total_attrs; header = tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0)); r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0)); inst = tc_MOV(tc, header, r0); inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) { inst = tc_OR(tc, tdst_offset(header, 0, 5), tsrc_rect(tsrc_offset(r0, 0, 5), TOY_RECT_010), tsrc_rect(tsrc_imm_ud(0xff00), TOY_RECT_010)); inst->exec_size = GEN6_EXECSIZE_1; inst->access_mode = GEN6_ALIGN_1; inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; } total_attrs = vs_collect_outputs(vcc, outs); sent_attrs = 0; while (sent_attrs < total_attrs) { struct toy_src desc; int mrf = vcc->first_free_mrf + 1, avail_mrf_for_attrs; int num_attrs, msg_len, i; bool eot; num_attrs = total_attrs - sent_attrs; eot = true; /* see if we need another message */ avail_mrf_for_attrs = vcc->last_free_mrf - mrf + 1; if (num_attrs > avail_mrf_for_attrs) { /* * From the Sandy Bridge PRM, volume 4 part 2, page 22: * * "Offset. This field specifies a destination offset (in 256-bit * units) from the start of the URB entry(s), as referenced by * URB Return Handle n, at which the data (if any) will be * written." * * As we need to offset the following messages, we must make sure * this one writes an even number of attributes. */ num_attrs = avail_mrf_for_attrs & ~1; eot = false; } if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) { /* do not forget about the header */ msg_len = 1 + num_attrs; } else { /* * From the Sandy Bridge PRM, volume 4 part 2, page 26: * * "At least 256 bits per vertex (512 bits total, M1 & M2) must * be written. Writing only 128 bits per vertex (256 bits * total, M1 only) results in UNDEFINED operation." * * "[DevSNB] Interleave writes must be in multiples of 256 per * vertex." * * That is, we must write or appear to write an even number of * attributes, starting from two. */ if (num_attrs % 2 && num_attrs == avail_mrf_for_attrs) { num_attrs--; eot = false; } msg_len = 1 + align(num_attrs, 2); } for (i = 0; i < num_attrs; i++) tc_MOV(tc, tdst(TOY_FILE_MRF, mrf++, 0), outs[sent_attrs + i]); assert(sent_attrs % 2 == 0); desc = tsrc_imm_mdesc_urb(tc, eot, msg_len, 0, eot, true, false, true, sent_attrs / 2, 0); tc_add2(tc, TOY_OPCODE_URB_WRITE, tdst_null(), tsrc_from(header), desc); sent_attrs += num_attrs; } }
static void fetch_position(struct fs_compile_context *fcc, struct toy_dst dst) { struct toy_compiler *tc = &fcc->tc; const struct toy_src src_z = tsrc(TOY_FILE_GRF, fcc->payloads[0].source_depth, 0); const struct toy_src src_w = tsrc(TOY_FILE_GRF, fcc->payloads[0].source_w, 0); const int fb_height = (fcc->variant->u.fs.fb_height) ? fcc->variant->u.fs.fb_height : 1; const bool origin_upper_left = (fcc->tgsi.props.fs_coord_origin == TGSI_FS_COORD_ORIGIN_UPPER_LEFT); const bool pixel_center_integer = (fcc->tgsi.props.fs_coord_pixel_center == TGSI_FS_COORD_PIXEL_CENTER_INTEGER); struct toy_src subspan_x, subspan_y; struct toy_dst tmp, tmp_uw; struct toy_dst real_dst[4]; tdst_transpose(dst, real_dst); subspan_x = tsrc_uw(tsrc(TOY_FILE_GRF, 1, 2 * 4)); subspan_x = tsrc_rect(subspan_x, TOY_RECT_240); subspan_y = tsrc_offset(subspan_x, 0, 1); tmp_uw = tdst_uw(tc_alloc_tmp(tc)); tmp = tc_alloc_tmp(tc); /* X */ tc_ADD(tc, tmp_uw, subspan_x, tsrc_imm_v(0x10101010)); tc_MOV(tc, tmp, tsrc_from(tmp_uw)); if (pixel_center_integer) tc_MOV(tc, real_dst[0], tsrc_from(tmp)); else tc_ADD(tc, real_dst[0], tsrc_from(tmp), tsrc_imm_f(0.5f)); /* Y */ tc_ADD(tc, tmp_uw, subspan_y, tsrc_imm_v(0x11001100)); tc_MOV(tc, tmp, tsrc_from(tmp_uw)); if (origin_upper_left && pixel_center_integer) { tc_MOV(tc, real_dst[1], tsrc_from(tmp)); } else { struct toy_src y = tsrc_from(tmp); float offset = 0.0f; if (!pixel_center_integer) offset += 0.5f; if (!origin_upper_left) { offset += (float) (fb_height - 1); y = tsrc_negate(y); } tc_ADD(tc, real_dst[1], y, tsrc_imm_f(offset)); } /* Z and W */ tc_MOV(tc, real_dst[2], src_z); tc_INV(tc, real_dst[3], src_w); }
/** * Emit instructions to write the color buffers (and the depth buffer). */ static void fs_write_fb(struct fs_compile_context *fcc) { struct toy_compiler *tc = &fcc->tc; int base_mrf = fcc->first_free_mrf; const struct toy_dst header = tdst_ud(tdst(TOY_FILE_MRF, base_mrf, 0)); bool header_present = false; struct toy_src desc; unsigned msg_type, ctrl; int color_slots[ILO_MAX_DRAW_BUFFERS], num_cbufs; int pos_slot = -1, cbuf, i; for (i = 0; i < Elements(color_slots); i++) color_slots[i] = -1; for (i = 0; i < fcc->tgsi.num_outputs; i++) { if (fcc->tgsi.outputs[i].semantic_name == TGSI_SEMANTIC_COLOR) { assert(fcc->tgsi.outputs[i].semantic_index < Elements(color_slots)); color_slots[fcc->tgsi.outputs[i].semantic_index] = i; } else if (fcc->tgsi.outputs[i].semantic_name == TGSI_SEMANTIC_POSITION) { pos_slot = i; } } num_cbufs = fcc->variant->u.fs.num_cbufs; /* still need to send EOT (and probably depth) */ if (!num_cbufs) num_cbufs = 1; /* we need the header to specify the pixel mask or render target */ if (fcc->tgsi.uses_kill || num_cbufs > 1) { const struct toy_src r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0)); struct toy_inst *inst; inst = tc_MOV(tc, header, r0); inst->mask_ctrl = BRW_MASK_DISABLE; base_mrf += fcc->num_grf_per_vrf; /* this is a two-register header */ if (fcc->dispatch_mode == GEN6_WM_8_DISPATCH_ENABLE) { inst = tc_MOV(tc, tdst_offset(header, 1, 0), tsrc_offset(r0, 1, 0)); inst->mask_ctrl = BRW_MASK_DISABLE; base_mrf += fcc->num_grf_per_vrf; } header_present = true; } for (cbuf = 0; cbuf < num_cbufs; cbuf++) { const int slot = color_slots[(fcc->tgsi.props.fs_color0_writes_all_cbufs) ? 0 : cbuf]; int mrf = base_mrf, vrf; struct toy_src src[4]; if (slot >= 0) { const unsigned undefined_mask = fcc->tgsi.outputs[slot].undefined_mask; const int index = fcc->tgsi.outputs[slot].index; vrf = toy_tgsi_get_vrf(&fcc->tgsi, TGSI_FILE_OUTPUT, 0, index); if (vrf >= 0) { const struct toy_src tmp = tsrc(TOY_FILE_VRF, vrf, 0); tsrc_transpose(tmp, src); } else { /* use (0, 0, 0, 0) */ tsrc_transpose(tsrc_imm_f(0.0f), src); } for (i = 0; i < 4; i++) { const struct toy_dst dst = tdst(TOY_FILE_MRF, mrf, 0); if (undefined_mask & (1 << i)) src[i] = tsrc_imm_f(0.0f); tc_MOV(tc, dst, src[i]); mrf += fcc->num_grf_per_vrf; } } else { /* use (0, 0, 0, 0) */ for (i = 0; i < 4; i++) { const struct toy_dst dst = tdst(TOY_FILE_MRF, mrf, 0); tc_MOV(tc, dst, tsrc_imm_f(0.0f)); mrf += fcc->num_grf_per_vrf; } } /* select BLEND_STATE[rt] */ if (cbuf > 0) { struct toy_inst *inst; inst = tc_MOV(tc, tdst_offset(header, 0, 2), tsrc_imm_ud(cbuf)); inst->mask_ctrl = BRW_MASK_DISABLE; inst->exec_size = BRW_EXECUTE_1; inst->src[0].rect = TOY_RECT_010; } if (cbuf == 0 && pos_slot >= 0) { const int index = fcc->tgsi.outputs[pos_slot].index; const struct toy_dst dst = tdst(TOY_FILE_MRF, mrf, 0); struct toy_src src[4]; int vrf; vrf = toy_tgsi_get_vrf(&fcc->tgsi, TGSI_FILE_OUTPUT, 0, index); if (vrf >= 0) { const struct toy_src tmp = tsrc(TOY_FILE_VRF, vrf, 0); tsrc_transpose(tmp, src); } else { /* use (0, 0, 0, 0) */ tsrc_transpose(tsrc_imm_f(0.0f), src); } /* only Z */ tc_MOV(tc, dst, src[2]); mrf += fcc->num_grf_per_vrf; } msg_type = (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE) ? BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE : BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; ctrl = (cbuf == num_cbufs - 1) << 12 | msg_type << 8; desc = tsrc_imm_mdesc_data_port(tc, cbuf == num_cbufs - 1, mrf - fcc->first_free_mrf, 0, header_present, false, GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE, ctrl, ILO_WM_DRAW_SURFACE(cbuf)); tc_add2(tc, TOY_OPCODE_FB_WRITE, tdst_null(), tsrc(TOY_FILE_MRF, fcc->first_free_mrf, 0), desc); } }