static int twl4030_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
unsigned char alarm_data[ALL_TIME_REGS + 1];
int ret;
/* Month range is 01..12 */
alm->time.tm_mon++;
alarm_data[1] = BIN2BCD(alm->time.tm_sec);
alarm_data[2] = BIN2BCD(alm->time.tm_min);
alarm_data[3] = BIN2BCD(alm->time.tm_hour);
alarm_data[4] = BIN2BCD(alm->time.tm_mday);
alarm_data[5] = BIN2BCD(alm->time.tm_mon);
alarm_data[6] = BIN2BCD(alm->time.tm_year);
/* update all the alarm registers in one shot */
ret = twl4030_i2c_write(TWL4030_MODULE_RTC, alarm_data,
REG_ALARM_SECONDS_REG, ALL_TIME_REGS);
if (ret) {
printk(KERN_ERR "twl4030: twl4030_i2c_write error.\n");
goto out;
}
ret = twl4030_rtc_alarm_irq_set_state(dev, alm->enabled);
out:
return ret;
}
static int twl4030_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
unsigned char alarm_data[ALL_TIME_REGS + 1];
int ret;
ret = twl4030_rtc_alarm_irq_set_state(0);
if (ret)
goto out;
alarm_data[1] = bin2bcd(alm->time.tm_sec);
alarm_data[2] = bin2bcd(alm->time.tm_min);
alarm_data[3] = bin2bcd(alm->time.tm_hour);
alarm_data[4] = bin2bcd(alm->time.tm_mday);
alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
alarm_data[6] = bin2bcd(alm->time.tm_year - 100);
/* update all the alarm registers in one shot */
ret = twl4030_i2c_write(TWL4030_MODULE_RTC, alarm_data,
REG_ALARM_SECONDS_REG, ALL_TIME_REGS);
if (ret) {
dev_err(dev, "rtc_set_alarm error %d\n", ret);
goto out;
}
if (alm->enabled)
ret = twl4030_rtc_alarm_irq_set_state(1);
out:
return ret;
}
/**
* twl4030_i2c_write_u8 - Writes a 8 bit register in TWL4030
* @mod_no: module number
* @value: the value to be written 8 bit
* @reg: register address (just offset will do)
*
* Returns result of operation - 0 is success
*/
int twl4030_i2c_write_u8(u8 mod_no, u8 value, u8 reg)
{
/* 2 bytes offset 1 contains the data offset 0 is used by i2c_write */
u8 temp_buffer[2] = { 0 };
/* offset 1 contains the data */
temp_buffer[1] = value;
return twl4030_i2c_write(mod_no, temp_buffer, reg, 1);
}
int twl4030_enable_dvi(disp_adapter_t *adapter)
{
unsigned speed;
unsigned char b;
int err;
/*
* Open the I2C controller device for the codec
*/
fd = open(TWL4030_I2C_DEVICE, O_RDWR);
if (fd == NULL) {
perror("open");
return -1;
}
printf("\n Enable DVI output on BeagleBoard-xM\n");
slogf(21,0,"Enable DVI output on BeagleBoard-xM\n" );
/*
* Set the I2C speed for the codec
*/
speed = TWL4030_I2C_SPEED;
err = devctl(fd, DCMD_I2C_SET_BUS_SPEED, &speed, sizeof(speed), NULL);
if (err != EOK) {
return -1;
}
/* Set GPOI2 (DVI_PU) high, to power on the DVI */
// First set the direction. Read in the existing direction value
if (twl4030_i2c_read(TWL4030_ADDR_GRP4, 0x9B, &b))
return -1; // bail if the access fails
b |= (1 << 2);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP4, 0x9B, b);
// Now set the value high
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP4, 0xA4, (unsigned char)(1<<2));
return 0;
}
int twl4030_setup_graphics(disp_adapter_t *adapter)
{
unsigned speed;
int err;
/*
* Open the I2C controller device for the codec
*/
fd = open(TWL4030_I2C_DEVICE, O_RDWR);
if (fd == NULL) {
perror("open");
return -1;
}
printf("\n Setting up graphics \n");
slogf(21,0,"setting up graphics \n" );
/*
* Set the I2C speed for the codec
*/
speed = TWL4030_I2C_SPEED;
err = devctl(fd, DCMD_I2C_SET_BUS_SPEED, &speed, sizeof(speed), NULL);
if (err != EOK) {
return -1;
}
/* turn on LCD backlight */
//twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_LEDEN, 0x33);
//twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_LEDEN, 0x32);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMAON, 0x7F);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMAOFF, 0x7F);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMBON, 0x7F);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMBOFF, 0x7F);
/* configure VPLL2 for graphics */
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VAUX4_DEDICATED, TWL4030_ENABLE_VAUX4_DEDICATED);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VAUX4_DEV_GRP, TWL4030_ENABLE_VAUX4_DEV_GRP);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VPLL2_DEDICATED, TWL4030_ENABLE_VPLL2_DEDICATED);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VPLL2_DEV_GRP, TWL4030_ENABLE_VPLL2_DEV_GRP);
return 0;
}
static int twl4030_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
unsigned char save_control;
unsigned char rtc_data[ALL_TIME_REGS + 1];
int ret;
/* Month range is 01..12 */
tm->tm_mon++;
rtc_data[1] = BIN2BCD(tm->tm_sec);
rtc_data[2] = BIN2BCD(tm->tm_min);
rtc_data[3] = BIN2BCD(tm->tm_hour);
rtc_data[4] = BIN2BCD(tm->tm_mday);
rtc_data[5] = BIN2BCD(tm->tm_mon);
rtc_data[6] = BIN2BCD(tm->tm_year);
/* Stop RTC while updating the TC registers */
ret = twl4030_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
if (ret < 0)
goto out;
save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
twl4030_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
if (ret < 0)
goto out;
/* update all the alarm registers in one shot */
ret = twl4030_i2c_write(TWL4030_MODULE_RTC, rtc_data,
REG_SECONDS_REG, ALL_TIME_REGS);
if (ret < 0) {
printk(KERN_ERR "twl4030: twl4030_i2c_write error.\n");
goto out;
}
/* Start back RTC */
save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
ret = twl4030_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
out:
return ret;
}
static int twl4030_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
unsigned char save_control;
unsigned char rtc_data[ALL_TIME_REGS + 1];
int ret;
rtc_data[1] = bin2bcd(tm->tm_sec);
rtc_data[2] = bin2bcd(tm->tm_min);
rtc_data[3] = bin2bcd(tm->tm_hour);
rtc_data[4] = bin2bcd(tm->tm_mday);
rtc_data[5] = bin2bcd(tm->tm_mon + 1);
rtc_data[6] = bin2bcd(tm->tm_year - 100);
/* Stop RTC while updating the TC registers */
ret = twl4030_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
if (ret < 0)
goto out;
save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
twl4030_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
if (ret < 0)
goto out;
/* update all the time registers in one shot */
ret = twl4030_i2c_write(TWL4030_MODULE_RTC, rtc_data,
REG_SECONDS_REG, ALL_TIME_REGS);
if (ret < 0) {
dev_err(dev, "rtc_set_time error %d\n", ret);
goto out;
}
/* Start back RTC */
save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
ret = twl4030_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
out:
return ret;
}
int main( int argc, char *argv[] )
{
unsigned speed;
int err;
char machine_name[MACHINE_NAME_MAX_LEN];
/*
* Open the I2C controller device for the codec
*/
fd = open(TWL4030_I2C_DEVICE, O_RDWR);
if (fd == NULL) {
perror("open");
return -1;
}
/*
* Set the I2C speed for the codec
*/
speed = TWL4030_I2C_SPEED;
err = devctl(fd, DCMD_I2C_SET_BUS_SPEED, &speed, sizeof(speed), NULL);
if (err != EOK) {
return -1;
}
/* MMC SD power */
twl4030_i2c_write( TWL4030_ADDR_GRP1, TWL4030_NRESPWRON_DEV_GRP, 0x20);
twl4030_i2c_write( TWL4030_ADDR_GRP1, TWL4030_CLKEN_DEV_GRP, 0x2);
/* Audio*/
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x7A, 0x20);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x7D, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x8E, 0xE0);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x91, 0x05);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x01, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x02, 0xc0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x03, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x04, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x05, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x06, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x07, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x08, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x09, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x0a, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x0b, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x0c, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x0d, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x0e, 0x01);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x0f, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x10, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x11, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x12, 0x6c);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x13, 0x6c);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x14, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x15, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x16, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x17, 0x0c);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x18, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x19, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x1a, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x1b, 0x2b);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x1c, 0x2b);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x1d, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x1e, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x1f, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x20, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x21, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x22, 0x24);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x23, 0x0a);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x24, 0x42);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x25, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x26, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x27, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x28, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x29, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x2a, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x2b, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x2c, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x2d, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x2e, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x2f, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x30, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x31, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x32, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x33, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x34, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x35, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x36, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x37, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x38, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x39, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x3a, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x3b, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x3c, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x3d, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x3e, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x3f, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x40, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x41, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x42, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x43, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x44, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x45, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x46, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x47, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x48, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x49, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x4a, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x4b, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x4c, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x4d, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x4e, 0x0);
twl4030_i2c_write( TWL4030_ADDR_GRP4, 0x4f, 0x0);
/*misc_init_r*/
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x7a, 0x20);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x7d, 0x03);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x8E, 0xe0);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x91, 0x05);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x96, 0x20);
twl4030_i2c_write( TWL4030_ADDR_GRP1, 0x99, 0x03);
// Enable LEDB to blink on the xM
twl4030_i2c_write( TWL4030_ADDR_GRP2, TWL4030_LEDEN, 0x23);
/* turn on LCD backlight */
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_PWMBON, 0x3F);
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_PWMBOFF, 0x7F);
/* configure VPLL2 for graphics */
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX4_DEDICATED, TWL4030_ENABLE_VAUX4_DEDICATED);
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX4_DEV_GRP, TWL4030_ENABLE_VAUX4_DEV_GRP);
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VPLL2_DEDICATED, TWL4030_ENABLE_VPLL2_DEDICATED);
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VPLL2_DEV_GRP, TWL4030_ENABLE_VPLL2_DEV_GRP);
/* check if we have beagle C4 */
confstr(_CS_MACHINE, machine_name, MACHINE_NAME_MAX_LEN);
if(!strcmp(machine_name, "OMAP3530_BEAGLE_Rev_c4"))
{
// enable VDD_EHCI on VAUX2
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX2_DEDICATED, TWL4030_ENABLE_VAUX2_DEDICATED);
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX2_DEV_GRP, TWL4030_ENABLE_VAUX2_DEV_GRP);
}
if(!strcmp(machine_name, "OMAP3730_BEAGLE_Rev_xm_b"))
{
// enable VDD_EHCI on VAUX2
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX2_DEDICATED, TWL4030_ENABLE_VAUX2_DEDICATED);
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX2_DEV_GRP, TWL4030_ENABLE_VAUX2_DEV_GRP);
printf("xM enabling hub \n");
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_PWMBON, 0x0);
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_PWMBOFF, 0x0);
// We should really do a read/mody/write here not just a straight write
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_LEDEN, 0x32);
}
else if(!strcmp(machine_name, "OMAP3730_BEAGLE_Rev_xm_c"))
{
// enable VDD_EHCI on VAUX2
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX2_DEDICATED, TWL4030_ENABLE_VAUX2_DEDICATED);
twl4030_i2c_write(TWL4030_ADDR_GRP1, TWL4030_VAUX2_DEV_GRP, TWL4030_ENABLE_VAUX2_DEV_GRP);
printf("xM enabling hub \n");
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_PWMBON, 0x0);
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_PWMBOFF, 0x0);
// We should really do a read/mody/write here not just a straight write
twl4030_i2c_write(TWL4030_ADDR_GRP2, TWL4030_LEDEN, 0x33);
}
else if (!strcmp(machine_name, "OMAP3530_BEAGLE_Rev_xx"))
{
fprintf(stderr,"Warning: unrecognized BEAGLE revision.\n");
fprintf(stderr," VAUX2 is left at default and so EHCI may not work.\n");
}
close (fd);
exit( EXIT_SUCCESS );
}
