/* * Handle external interrupts */ void external_interrupt(struct pt_regs *regs) { u32 uic_msr; /* * Read masked interrupt status register to determine interrupt source */ uic_msr = mfdcr(UIC0MSR); #if (UIC_MAX > 1) if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) || (UIC_MASK(VECNUM_UIC1NCI) & uic_msr)) uic_interrupt(UIC1_DCR_BASE, 32); #endif #if (UIC_MAX > 2) if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) || (UIC_MASK(VECNUM_UIC2NCI) & uic_msr)) uic_interrupt(UIC2_DCR_BASE, 64); #endif #if (UIC_MAX > 3) if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) || (UIC_MASK(VECNUM_UIC3NCI) & uic_msr)) uic_interrupt(UIC3_DCR_BASE, 96); #endif mtdcr(UIC0SR, (uic_msr & UICB0_ALL)); if (uic_msr & ~(UICB0_ALL)) uic_interrupt(UIC0_DCR_BASE, 0); return; }
/* * Handle external interrupts */ void external_interrupt(struct pt_regs *regs) { u32 uic_msr; /* * Read masked interrupt status register to determine interrupt source */ uic_msr = mfdcr(uic0msr); mtdcr(uic0sr, (uic_msr & UICB0_ALL)); if (uic_msr & ~(UICB0_ALL)) { uic_interrupt(UIC0_DCR_BASE, 0); } return; }