static int usb_xhci_port_count_usb3(struct device *dev)
#endif
{
if (pch_is_lp()) {
/* LynxPoint-LP has 4 SS ports */
return 4;
}
/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
u8 *mem_base = usb_xhci_mem_base(dev);
u32 fus = read32(mem_base + XHCI_USB3FUS);
fus >>= XHCI_USB3FUS_SS_SHIFT;
fus &= XHCI_USB3FUS_SS_MASK;
switch (fus) {
case 3: return 0;
case 2: return 2;
case 1: return 4;
case 0:
default: return 6;
}
}
/* Handler for XHCI controller on entry to S3/S4/S5 */
void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < ACPI_S3)
return;
if (pch_is_lp()) {
/* Set D0 state */
reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
reg16 &= ~PWR_CTL_SET_MASK;
reg16 |= PWR_CTL_SET_D0;
pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
/* Clear PCI 0xB0[14:13] */
reg32 = pci_read_config32(dev, 0xb0);
reg32 &= ~((1 << 14) | (1 << 13));
pci_write_config32(dev, 0xb0, reg32);
/* Clear MMIO 0x816c[14,2] */
reg32 = read32(mem_base + 0x816c);
reg32 &= ~((1 << 14) | (1 << 2));
write32(mem_base + 0x816c, reg32);
/* Reset disconnected USB3 ports */
usb_xhci_reset_usb3(dev, 0);
/* Set MMIO 0x80e0[15] */
reg32 = read32(mem_base + 0x80e0);
reg32 |= (1 << 15);
write32(mem_base + 0x80e0, reg32);
}
/* Set D3Hot state and enable PME */
pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3);
pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_STATUS_PME);
pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME);
}
static void usb_xhci_reset_usb3(struct device *dev, int all)
#endif
{
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
/* Get mask of disabled ports */
port_disabled = pci_read_config32(dev, XHCI_USB3PDO);
/* Wait until all enabled ports are done polling */
for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
int complete = 1;
for (port = 0; port < port_count; port++) {
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
/* Read port link status field */
status = read32(mem_base + XHCI_USB3_PORTSC(port));
status &= XHCI_USB3_PORTSC_PLS;
if (status == XHCI_PLSR_POLLING)
complete = 0;
}
/* Exit if all ports not polling */
if (complete)
break;
udelay(XHCI_RESET_DELAY_US);
}
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
if (all || (status == XHCI_PLSR_RXDETECT ||
status == XHCI_PLSR_POLLING))
usb_xhci_reset_port_usb3(mem_base, port);
else
port_disabled |= 1 << port;
}
/* Wait for warm reset complete on all reset ports */
for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
int complete = 1;
for (port = 0; port < port_count; port++) {
/* Only check ports that were reset */
if (port_disabled & (1 << port))
continue;
/* Check if warm reset is complete */
status = read32(mem_base + XHCI_USB3_PORTSC(port));
if (!(status & XHCI_USB3_PORTSC_WRC))
complete = 0;
}
/* Check for warm reset complete in any port */
if (complete)
break;
udelay(XHCI_RESET_DELAY_US);
}
/* Clear port change status bits */
for (port = 0; port < port_count; port++)
usb_xhci_reset_status_usb3(mem_base, port);
}
static void usb_xhci_init(device_t dev)
{
u32 reg32;
u16 reg16;
u32 mem_base = usb_xhci_mem_base(dev);
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */
reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
reg16 &= ~PWR_CTL_SET_MASK;
reg16 |= PWR_CTL_SET_D0;
pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
/* Enable clock gating first */
usb_xhci_clock_gating(dev);
reg32 = read32(mem_base + 0x8144);
if (pch_is_lp()) {
/* XHCIBAR + 8144h[8,7,6] = 111b */
reg32 |= (1 << 8) | (1 << 7) | (1 << 6);
} else {
/* XHCIBAR + 8144h[8,7,6] = 100b */
reg32 &= ~((1 << 7) | (1 << 6));
reg32 |= (1 << 8);
}
write32(mem_base + 0x8144, reg32);
if (pch_is_lp()) {
/* XHCIBAR + 816Ch[19:0] = 000e0038h */
reg32 = read32(mem_base + 0x816c);
reg32 &= ~0x000fffff;
reg32 |= 0x000e0038;
write32(mem_base + 0x816c, reg32);
/* D20:F0:B0h[17,14,13] = 100b */
reg32 = pci_read_config32(dev, 0xb0);
reg32 &= ~((1 << 14) | (1 << 13));
reg32 |= (1 << 17);
pci_write_config32(dev, 0xb0, reg32);
}
reg32 = pci_read_config32(dev, 0x50);
if (pch_is_lp()) {
/* D20:F0:50h[28:0] = 0FCE2E5Fh */
reg32 &= ~0x1fffffff;
reg32 |= 0x0fce2e5f;
} else {
/* D20:F0:50h[26:0] = 07886E9Fh */
reg32 &= ~0x07ffffff;
reg32 |= 0x07886e9f;
}
pci_write_config32(dev, 0x50, reg32);
/* D20:F0:44h[31] = 1 (Access Control Bit) */
reg32 = pci_read_config32(dev, 0x44);
reg32 |= (1 << 31);
pci_write_config32(dev, 0x44, reg32);
/* D20:F0:40h[31,23] = 10b (OC Configuration Done) */
reg32 = pci_read_config32(dev, 0x40);
reg32 &= ~(1 << 23); /* unsupported request */
reg32 |= (1 << 31);
pci_write_config32(dev, 0x40, reg32);
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type == 3) {
/* Reset ports that are disabled or
* polling before returning to the OS. */
usb_xhci_reset_usb3(dev, 0);
} else
#endif
/* Route all ports to XHCI */
if (config->xhci_default)
outb(0xca, 0xb2);
}
static void usb_xhci_init(device_t dev)
{
u32 reg32;
u16 reg16;
u32 mem_base = usb_xhci_mem_base(dev);
/* D20:F0:74h[1:0] = 00b (set D0 state) */
reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
reg16 &= ~PWR_CTL_SET_MASK;
reg16 |= PWR_CTL_SET_D0;
pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
/* Enable clock gating first */
usb_xhci_clock_gating(dev);
reg32 = read32(mem_base + 0x8144);
if (pch_is_lp()) {
/* XHCIBAR + 8144h[8,7,6] = 111b */
reg32 |= (1 << 8) | (1 << 7) | (1 << 6);
} else {
/* XHCIBAR + 8144h[8,7,6] = 100b */
reg32 &= ~((1 << 7) | (1 << 6));
reg32 |= (1 << 8);
}
write32(mem_base + 0x8144, reg32);
if (pch_is_lp()) {
/* XHCIBAR + 816Ch[19:0] = 000e0038h */
reg32 = read32(mem_base + 0x816c);
reg32 &= ~0x000fffff;
reg32 |= 0x000e0038;
write32(mem_base + 0x816c, reg32);
/* D20:F0:B0h[17,14,13] = 100b */
reg32 = pci_read_config32(dev, 0xb0);
reg32 &= ~((1 << 14) | (1 << 13));
reg32 |= (1 << 17);
pci_write_config32(dev, 0xb0, reg32);
}
reg32 = pci_read_config32(dev, 0x50);
if (pch_is_lp()) {
/* D20:F0:50h[28:0] = 0FCE2E5Fh */
reg32 &= ~0x1fffffff;
reg32 |= 0x0fce2e5f;
} else {
/* D20:F0:50h[26:0] = 07886E9Fh */
reg32 &= ~0x07ffffff;
reg32 |= 0x07886e9f;
}
pci_write_config32(dev, 0x50, reg32);
/* D20:F0:44h[31] = 1 (Access Control Bit) */
reg32 = pci_read_config32(dev, 0x44);
reg32 |= (1 << 31);
pci_write_config32(dev, 0x44, reg32);
/* D20:F0:40h[31,23] = 10b (OC Configuration Done) */
reg32 = pci_read_config32(dev, 0x40);
reg32 &= ~(1 << 23); /* unsupported request */
reg32 |= (1 << 31);
pci_write_config32(dev, 0x40, reg32);
/* Enable ports that are disabled before returning to OS */
if (acpi_is_wakeup_s3())
usb_xhci_enable_ports_usb3(dev);
}
/* Re-enable ports that are disabled */
static void usb_xhci_enable_ports_usb3(device_t dev)
{
#if CONFIG_FINALIZE_USB_ROUTE_XHCI
int port;
u32 portsc, status, disabled;
u32 mem_base = usb_xhci_mem_base(dev);
int port_count = usb_xhci_port_count_usb3(dev);
u8 port_reset = 0;
int timeout;
if (!mem_base || !port_count)
return;
/* Get port disable override map */
disabled = pci_read_config32(dev, XHCI_USB3PDO);
for (port = 0; port < port_count; port++) {
/* Skip overridden ports */
if (disabled & (1 << port))
continue;
portsc = mem_base + XHCI_USB3_PORTSC(port);
status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
switch (status) {
case XHCI_PLSR_RXDETECT:
/* Clear change status */
printk(BIOS_DEBUG, "usb_xhci reset status %d\n", port);
usb_xhci_reset_status_usb3(mem_base, port);
break;
case XHCI_PLSR_DISABLED:
default:
/* Reset port */
printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port);
usb_xhci_reset_port_usb3(mem_base, port);
port_reset |= 1 << port;
break;
}
}
if (!port_reset)
return;
/* Wait for warm reset complete on all reset ports */
for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) {
int complete = 1;
for (port = 0; port < port_count; port++) {
/* Only check ports that were reset */
if (!(port_reset & (1 << port)))
continue;
/* Check if warm reset is complete */
status = read32(mem_base + XHCI_USB3_PORTSC(port));
if (!(status & XHCI_USB3_PORTSC_WRC))
complete = 0;
}
/* Check for warm reset complete in any port */
if (complete)
break;
udelay(XHCI_RESET_DELAY_US);
}
/* Enable ports that were reset */
for (port = 0; port < port_count; port++) {
/* Only check ports that were reset */
if (!(port_reset & (1 << port)))
continue;
/* Transition to enabled */
portsc = mem_base + XHCI_USB3_PORTSC(port);
status = read32(portsc);
status &= ~(XHCI_USB3_PORTSC_PLS | XHCI_USB3_PORTSC_PED);
status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS;
write32(portsc, status);
}
#endif
}
