static struct ureg_dst alloc_temporary( struct ureg_program *ureg, boolean local ) { unsigned i; /* Look for a released temporary. */ for (i = util_bitmask_get_first_index(ureg->free_temps); i != UTIL_BITMASK_INVALID_INDEX; i = util_bitmask_get_next_index(ureg->free_temps, i + 1)) { if (util_bitmask_get(ureg->local_temps, i) == local) break; } /* Or allocate a new one. */ if (i == UTIL_BITMASK_INVALID_INDEX) { i = ureg->nr_temps++; if (local) util_bitmask_set(ureg->local_temps, i); /* Start a new declaration when the local flag changes */ if (!i || util_bitmask_get(ureg->local_temps, i - 1) != local) util_bitmask_set(ureg->decl_temps, i); } util_bitmask_clear(ureg->free_temps, i); return ureg_dst_register( TGSI_FILE_TEMPORARY, i ); }
static void svga_delete_vertex_elements_state(struct pipe_context *pipe, void *state) { struct svga_context *svga = svga_context(pipe); struct svga_velems_state *velems = (struct svga_velems_state *) state; if (svga_have_vgpu10(svga)) { enum pipe_error ret; svga_hwtnl_flush_retry(svga); ret = SVGA3D_vgpu10_DestroyElementLayout(svga->swc, velems->id); if (ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_vgpu10_DestroyElementLayout(svga->swc, velems->id); assert(ret == PIPE_OK); } if (velems->id == svga->state.hw_draw.layout_id) svga->state.hw_draw.layout_id = SVGA3D_INVALID_ID; util_bitmask_clear(svga->input_element_object_id_bm, velems->id); velems->id = SVGA3D_INVALID_ID; } FREE(velems); }
static void svga_delete_fs_state(struct pipe_context *pipe, void *shader) { struct svga_context *svga = svga_context(pipe); struct svga_fragment_shader *fs = (struct svga_fragment_shader *) shader; struct svga_shader_result *result, *tmp; enum pipe_error ret; svga_hwtnl_flush_retry( svga ); draw_delete_fragment_shader(svga->swtnl.draw, fs->draw_shader); for (result = fs->base.results; result; result = tmp ) { tmp = result->next; ret = SVGA3D_DestroyShader(svga->swc, result->id, SVGA3D_SHADERTYPE_PS ); if(ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_DestroyShader(svga->swc, result->id, SVGA3D_SHADERTYPE_PS ); assert(ret == PIPE_OK); } util_bitmask_clear( svga->fs_bm, result->id ); svga_destroy_shader_result( result ); /* * Remove stale references to this result to ensure a new result on the * same address will be detected as a change. */ if(result == svga->state.hw_draw.fs) svga->state.hw_draw.fs = NULL; } FREE((void *)fs->base.tokens); FREE(fs); }
static enum pipe_error compile_vs( struct svga_context *svga, struct svga_vertex_shader *vs, const struct svga_vs_compile_key *key, struct svga_shader_result **out_result ) { struct svga_shader_result *result; enum pipe_error ret = PIPE_ERROR; result = svga_translate_vertex_program( vs, key ); if (result == NULL) { ret = PIPE_ERROR_OUT_OF_MEMORY; goto fail; } result->id = util_bitmask_add(svga->vs_bm); if(result->id == UTIL_BITMASK_INVALID_INDEX) { ret = PIPE_ERROR_OUT_OF_MEMORY; goto fail; } ret = SVGA3D_DefineShader(svga->swc, result->id, SVGA3D_SHADERTYPE_VS, result->tokens, result->nr_tokens * sizeof result->tokens[0]); if (ret) goto fail; *out_result = result; result->next = vs->base.results; vs->base.results = result; return PIPE_OK; fail: if (result) { if (result->id != UTIL_BITMASK_INVALID_INDEX) util_bitmask_clear( svga->vs_bm, result->id ); svga_destroy_shader_result( result ); } return ret; }
void svga_delete_stream_output(struct svga_context *svga, struct svga_stream_output *streamout) { enum pipe_error ret; SVGA_DBG(DEBUG_STREAMOUT, "%s streamout=0x%x\n", __FUNCTION__, streamout); assert(svga_have_vgpu10(svga)); assert(streamout != NULL); ret = SVGA3D_vgpu10_DestroyStreamOutput(svga->swc, streamout->id); if (ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_vgpu10_DestroyStreamOutput(svga->swc, streamout->id); } /* Release the ID */ util_bitmask_clear(svga->stream_output_id_bm, streamout->id); /* Free streamout structure */ FREE(streamout); }
/** * Define a vgpu10 blend state object for the given * svga blend state. */ static void define_blend_state_object(struct svga_context *svga, struct svga_blend_state *bs) { SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS]; unsigned try; int i; assert(svga_have_vgpu10(svga)); bs->id = util_bitmask_add(svga->blend_object_id_bm); for (i = 0; i < SVGA3D_DX_MAX_RENDER_TARGETS; i++) { perRT[i].blendEnable = bs->rt[i].blend_enable; perRT[i].srcBlend = bs->rt[i].srcblend; perRT[i].destBlend = bs->rt[i].dstblend; perRT[i].blendOp = bs->rt[i].blendeq; perRT[i].srcBlendAlpha = bs->rt[i].srcblend_alpha; perRT[i].destBlendAlpha = bs->rt[i].dstblend_alpha; perRT[i].blendOpAlpha = bs->rt[i].blendeq_alpha; perRT[i].renderTargetWriteMask = bs->rt[i].writemask; perRT[i].logicOpEnable = 0; perRT[i].logicOp = SVGA3D_LOGICOP_COPY; assert(perRT[i].srcBlend == perRT[0].srcBlend); } /* Loop in case command buffer is full and we need to flush and retry */ for (try = 0; try < 2; try++) { enum pipe_error ret; ret = SVGA3D_vgpu10_DefineBlendState(svga->swc, bs->id, bs->alpha_to_coverage, bs->independent_blend_enable, perRT); if (ret == PIPE_OK) return; svga_context_flush(svga, NULL); } } static void * svga_create_blend_state(struct pipe_context *pipe, const struct pipe_blend_state *templ) { struct svga_context *svga = svga_context(pipe); struct svga_blend_state *blend = CALLOC_STRUCT( svga_blend_state ); unsigned i; if (!blend) return NULL; /* Fill in the per-rendertarget blend state. We currently only * support independent blend enable and colormask per render target. */ for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) { /* No way to set this in SVGA3D, and no way to correctly implement it on * top of D3D9 API. Instead we try to simulate with various blend modes. */ if (templ->logicop_enable) { switch (templ->logicop_func) { case PIPE_LOGICOP_XOR: case PIPE_LOGICOP_INVERT: blend->need_white_fragments = TRUE; blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_ONE; blend->rt[i].dstblend = SVGA3D_BLENDOP_ONE; blend->rt[i].blendeq = SVGA3D_BLENDEQ_SUBTRACT; break; case PIPE_LOGICOP_CLEAR: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_ZERO; blend->rt[i].dstblend = SVGA3D_BLENDOP_ZERO; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MINIMUM; break; case PIPE_LOGICOP_COPY: blend->rt[i].blend_enable = FALSE; blend->rt[i].srcblend = SVGA3D_BLENDOP_ONE; blend->rt[i].dstblend = SVGA3D_BLENDOP_ZERO; blend->rt[i].blendeq = SVGA3D_BLENDEQ_ADD; break; case PIPE_LOGICOP_COPY_INVERTED: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_INVSRCCOLOR; blend->rt[i].dstblend = SVGA3D_BLENDOP_ZERO; blend->rt[i].blendeq = SVGA3D_BLENDEQ_ADD; break; case PIPE_LOGICOP_NOOP: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_ZERO; blend->rt[i].dstblend = SVGA3D_BLENDOP_DESTCOLOR; blend->rt[i].blendeq = SVGA3D_BLENDEQ_ADD; break; case PIPE_LOGICOP_SET: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_ONE; blend->rt[i].dstblend = SVGA3D_BLENDOP_ONE; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MAXIMUM; break; case PIPE_LOGICOP_AND: /* Approximate with minimum - works for the 0 & anything case: */ blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_SRCCOLOR; blend->rt[i].dstblend = SVGA3D_BLENDOP_DESTCOLOR; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MINIMUM; break; case PIPE_LOGICOP_AND_REVERSE: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_SRCCOLOR; blend->rt[i].dstblend = SVGA3D_BLENDOP_INVDESTCOLOR; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MINIMUM; break; case PIPE_LOGICOP_AND_INVERTED: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_INVSRCCOLOR; blend->rt[i].dstblend = SVGA3D_BLENDOP_DESTCOLOR; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MINIMUM; break; case PIPE_LOGICOP_OR: /* Approximate with maximum - works for the 1 | anything case: */ blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_SRCCOLOR; blend->rt[i].dstblend = SVGA3D_BLENDOP_DESTCOLOR; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MAXIMUM; break; case PIPE_LOGICOP_OR_REVERSE: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_SRCCOLOR; blend->rt[i].dstblend = SVGA3D_BLENDOP_INVDESTCOLOR; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MAXIMUM; break; case PIPE_LOGICOP_OR_INVERTED: blend->rt[i].blend_enable = TRUE; blend->rt[i].srcblend = SVGA3D_BLENDOP_INVSRCCOLOR; blend->rt[i].dstblend = SVGA3D_BLENDOP_DESTCOLOR; blend->rt[i].blendeq = SVGA3D_BLENDEQ_MAXIMUM; break; case PIPE_LOGICOP_NAND: case PIPE_LOGICOP_NOR: case PIPE_LOGICOP_EQUIV: /* Fill these in with plausible values */ blend->rt[i].blend_enable = FALSE; blend->rt[i].srcblend = SVGA3D_BLENDOP_ONE; blend->rt[i].dstblend = SVGA3D_BLENDOP_ZERO; blend->rt[i].blendeq = SVGA3D_BLENDEQ_ADD; break; default: assert(0); break; } blend->rt[i].srcblend_alpha = blend->rt[i].srcblend; blend->rt[i].dstblend_alpha = blend->rt[i].dstblend; blend->rt[i].blendeq_alpha = blend->rt[i].blendeq; if (templ->logicop_func == PIPE_LOGICOP_XOR) { pipe_debug_message(&svga->debug.callback, CONFORMANCE, "XOR logicop mode has limited support"); } else if (templ->logicop_func != PIPE_LOGICOP_COPY) { pipe_debug_message(&svga->debug.callback, CONFORMANCE, "general logicops are not supported"); } } else { /* Note: the vgpu10 device does not yet support independent * blend terms per render target. Target[0] always specifies the * blending terms. */ if (templ->independent_blend_enable || templ->rt[0].blend_enable) { /* always use the 0th target's blending terms for now */ blend->rt[i].srcblend = svga_translate_blend_factor(svga, templ->rt[0].rgb_src_factor); blend->rt[i].dstblend = svga_translate_blend_factor(svga, templ->rt[0].rgb_dst_factor); blend->rt[i].blendeq = svga_translate_blend_func(templ->rt[0].rgb_func); blend->rt[i].srcblend_alpha = svga_translate_blend_factor(svga, templ->rt[0].alpha_src_factor); blend->rt[i].dstblend_alpha = svga_translate_blend_factor(svga, templ->rt[0].alpha_dst_factor); blend->rt[i].blendeq_alpha = svga_translate_blend_func(templ->rt[0].alpha_func); if (blend->rt[i].srcblend_alpha != blend->rt[i].srcblend || blend->rt[i].dstblend_alpha != blend->rt[i].dstblend || blend->rt[i].blendeq_alpha != blend->rt[i].blendeq) { blend->rt[i].separate_alpha_blend_enable = TRUE; } } else { /* disabled - default blend terms */ blend->rt[i].srcblend = SVGA3D_BLENDOP_ONE; blend->rt[i].dstblend = SVGA3D_BLENDOP_ZERO; blend->rt[i].blendeq = SVGA3D_BLENDEQ_ADD; blend->rt[i].srcblend_alpha = SVGA3D_BLENDOP_ONE; blend->rt[i].dstblend_alpha = SVGA3D_BLENDOP_ZERO; blend->rt[i].blendeq_alpha = SVGA3D_BLENDEQ_ADD; } if (templ->independent_blend_enable) { blend->rt[i].blend_enable = templ->rt[i].blend_enable; } else { blend->rt[i].blend_enable = templ->rt[0].blend_enable; } } /* Some GL blend modes are not supported by the VGPU9 device (there's * no equivalent of PIPE_BLENDFACTOR_[INV_]CONST_ALPHA). * When we set this flag, we copy the constant blend alpha value * to the R, G, B components. * This works as long as the src/dst RGB blend factors doesn't use * PIPE_BLENDFACTOR_CONST_COLOR and PIPE_BLENDFACTOR_CONST_ALPHA * at the same time. There's no work-around for that. */ if (!svga_have_vgpu10(svga)) { if (templ->rt[0].rgb_src_factor == PIPE_BLENDFACTOR_CONST_ALPHA || templ->rt[0].rgb_dst_factor == PIPE_BLENDFACTOR_CONST_ALPHA || templ->rt[0].rgb_src_factor == PIPE_BLENDFACTOR_INV_CONST_ALPHA || templ->rt[0].rgb_dst_factor == PIPE_BLENDFACTOR_INV_CONST_ALPHA) { blend->blend_color_alpha = TRUE; } } if (templ->independent_blend_enable) { blend->rt[i].writemask = templ->rt[i].colormask; } else { blend->rt[i].writemask = templ->rt[0].colormask; } } blend->independent_blend_enable = templ->independent_blend_enable; blend->alpha_to_coverage = templ->alpha_to_coverage; if (svga_have_vgpu10(svga)) { define_blend_state_object(svga, blend); } svga->hud.num_blend_objects++; SVGA_STATS_COUNT_INC(svga_screen(svga->pipe.screen)->sws, SVGA_STATS_COUNT_BLENDSTATE); return blend; } static void svga_bind_blend_state(struct pipe_context *pipe, void *blend) { struct svga_context *svga = svga_context(pipe); svga->curr.blend = (struct svga_blend_state*)blend; svga->dirty |= SVGA_NEW_BLEND; } static void svga_delete_blend_state(struct pipe_context *pipe, void *blend) { struct svga_context *svga = svga_context(pipe); struct svga_blend_state *bs = (struct svga_blend_state *) blend; if (bs->id != SVGA3D_INVALID_ID) { enum pipe_error ret; ret = SVGA3D_vgpu10_DestroyBlendState(svga->swc, bs->id); if (ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_vgpu10_DestroyBlendState(svga->swc, bs->id); assert(ret == PIPE_OK); } if (bs->id == svga->state.hw_draw.blend_id) svga->state.hw_draw.blend_id = SVGA3D_INVALID_ID; util_bitmask_clear(svga->blend_object_id_bm, bs->id); bs->id = SVGA3D_INVALID_ID; } FREE(blend); svga->hud.num_blend_objects--; } static void svga_set_blend_color( struct pipe_context *pipe, const struct pipe_blend_color *blend_color ) { struct svga_context *svga = svga_context(pipe); svga->curr.blend_color = *blend_color; svga->dirty |= SVGA_NEW_BLEND_COLOR; } void svga_init_blend_functions( struct svga_context *svga ) { svga->pipe.create_blend_state = svga_create_blend_state; svga->pipe.bind_blend_state = svga_bind_blend_state; svga->pipe.delete_blend_state = svga_delete_blend_state; svga->pipe.set_blend_color = svga_set_blend_color; }
static void define_rasterizer_object(struct svga_context *svga, struct svga_rasterizer_state *rast) { unsigned fill_mode = translate_fill_mode(rast->templ.fill_front); unsigned cull_mode = translate_cull_mode(rast->templ.cull_face); int depth_bias = rast->templ.offset_units; float slope_scaled_depth_bias = rast->templ.offset_scale; float depth_bias_clamp = 0.0; /* XXX fix me */ unsigned try; const float line_width = rast->templ.line_width > 0.0f ? rast->templ.line_width : 1.0f; const uint8 line_factor = rast->templ.line_stipple_enable ? rast->templ.line_stipple_factor : 0; const uint16 line_pattern = rast->templ.line_stipple_enable ? rast->templ.line_stipple_pattern : 0; rast->id = util_bitmask_add(svga->rast_object_id_bm); if (rast->templ.fill_front != rast->templ.fill_back) { /* The VGPU10 device can't handle different front/back fill modes. * We'll handle that with a swtnl/draw fallback. But we need to * make sure we always fill triangles in that case. */ fill_mode = SVGA3D_FILLMODE_FILL; } for (try = 0; try < 2; try++) { enum pipe_error ret = SVGA3D_vgpu10_DefineRasterizerState(svga->swc, rast->id, fill_mode, cull_mode, rast->templ.front_ccw, depth_bias, depth_bias_clamp, slope_scaled_depth_bias, rast->templ.depth_clip, rast->templ.scissor, rast->templ.multisample, rast->templ.line_smooth, line_width, rast->templ.line_stipple_enable, line_factor, line_pattern, !rast->templ.flatshade_first); if (ret == PIPE_OK) return; svga_context_flush(svga, NULL); } } static void * svga_create_rasterizer_state(struct pipe_context *pipe, const struct pipe_rasterizer_state *templ) { struct svga_context *svga = svga_context(pipe); struct svga_rasterizer_state *rast = CALLOC_STRUCT( svga_rasterizer_state ); struct svga_screen *screen = svga_screen(pipe->screen); /* need this for draw module. */ rast->templ = *templ; /* light_twoside - XXX: need fragment shader variant */ /* poly_smooth - XXX: no fallback available */ /* poly_stipple_enable - draw module */ /* sprite_coord_enable - ? */ /* point_quad_rasterization - ? */ /* point_size_per_vertex - ? */ /* sprite_coord_mode - ??? */ /* flatshade_first - handled by index translation */ /* half_pixel_center - XXX - viewport code */ /* line_width - draw module */ /* fill_cw, fill_ccw - draw module or index translation */ rast->shademode = svga_translate_flatshade( templ->flatshade ); rast->cullmode = svga_translate_cullmode( templ->cull_face, templ->front_ccw ); rast->scissortestenable = templ->scissor; rast->multisampleantialias = templ->multisample; rast->antialiasedlineenable = templ->line_smooth; rast->lastpixel = templ->line_last_pixel; rast->pointsprite = templ->sprite_coord_enable != 0x0; if (templ->point_smooth) { /* For smooth points we need to generate fragments for at least * a 2x2 region. Otherwise the quad we draw may be too small and * we may generate no fragments at all. */ rast->pointsize = MAX2(2.0f, templ->point_size); } else { rast->pointsize = templ->point_size; } rast->hw_fillmode = PIPE_POLYGON_MODE_FILL; /* Use swtnl + decomposition implement these: */ if (templ->line_width <= screen->maxLineWidth) { /* pass line width to device */ rast->linewidth = MAX2(1.0F, templ->line_width); } else if (svga->debug.no_line_width) { /* nothing */ } else { /* use 'draw' pipeline for wide line */ rast->need_pipeline |= SVGA_PIPELINE_FLAG_LINES; rast->need_pipeline_lines_str = "line width"; } if (templ->line_stipple_enable) { if (screen->haveLineStipple || svga->debug.force_hw_line_stipple) { SVGA3dLinePattern lp; lp.repeat = templ->line_stipple_factor + 1; lp.pattern = templ->line_stipple_pattern; rast->linepattern = lp.uintValue; } else { /* use 'draw' module to decompose into short line segments */ rast->need_pipeline |= SVGA_PIPELINE_FLAG_LINES; rast->need_pipeline_lines_str = "line stipple"; } } if (!svga_have_vgpu10(svga) && templ->point_smooth) { rast->need_pipeline |= SVGA_PIPELINE_FLAG_POINTS; rast->need_pipeline_points_str = "smooth points"; } if (templ->line_smooth && !screen->haveLineSmooth) { /* * XXX: Enabling the pipeline slows down performance immensely, so ignore * line smooth state, where there is very little visual improvement. * Smooth lines will still be drawn for wide lines. */ #if 0 rast->need_pipeline |= SVGA_PIPELINE_FLAG_LINES; rast->need_pipeline_lines_str = "smooth lines"; #endif } { int fill_front = templ->fill_front; int fill_back = templ->fill_back; int fill = PIPE_POLYGON_MODE_FILL; boolean offset_front = util_get_offset(templ, fill_front); boolean offset_back = util_get_offset(templ, fill_back); boolean offset = FALSE; switch (templ->cull_face) { case PIPE_FACE_FRONT_AND_BACK: offset = FALSE; fill = PIPE_POLYGON_MODE_FILL; break; case PIPE_FACE_FRONT: offset = offset_front; fill = fill_front; break; case PIPE_FACE_BACK: offset = offset_back; fill = fill_back; break; case PIPE_FACE_NONE: if (fill_front != fill_back || offset_front != offset_back) { /* Always need the draw module to work out different * front/back fill modes: */ rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS; rast->need_pipeline_tris_str = "different front/back fillmodes"; } else { offset = offset_front; fill = fill_front; } break; default: assert(0); break; } /* Unfilled primitive modes aren't implemented on all virtual * hardware. We can do some unfilled processing with index * translation, but otherwise need the draw module: */ if (fill != PIPE_POLYGON_MODE_FILL && (templ->flatshade || templ->light_twoside || offset || templ->cull_face != PIPE_FACE_NONE)) { fill = PIPE_POLYGON_MODE_FILL; rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS; rast->need_pipeline_tris_str = "unfilled primitives with no index manipulation"; } /* If we are decomposing to lines, and lines need the pipeline, * then we also need the pipeline for tris. */ if (fill == PIPE_POLYGON_MODE_LINE && (rast->need_pipeline & SVGA_PIPELINE_FLAG_LINES)) { fill = PIPE_POLYGON_MODE_FILL; rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS; rast->need_pipeline_tris_str = "decomposing lines"; } /* Similarly for points: */ if (fill == PIPE_POLYGON_MODE_POINT && (rast->need_pipeline & SVGA_PIPELINE_FLAG_POINTS)) { fill = PIPE_POLYGON_MODE_FILL; rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS; rast->need_pipeline_tris_str = "decomposing points"; } if (offset) { rast->slopescaledepthbias = templ->offset_scale; rast->depthbias = templ->offset_units; } rast->hw_fillmode = fill; } if (rast->need_pipeline & SVGA_PIPELINE_FLAG_TRIS) { /* Turn off stuff which will get done in the draw module: */ rast->hw_fillmode = PIPE_POLYGON_MODE_FILL; rast->slopescaledepthbias = 0; rast->depthbias = 0; } if (0 && rast->need_pipeline) { debug_printf("svga: rast need_pipeline = 0x%x\n", rast->need_pipeline); debug_printf(" pnts: %s \n", rast->need_pipeline_points_str); debug_printf(" lins: %s \n", rast->need_pipeline_lines_str); debug_printf(" tris: %s \n", rast->need_pipeline_tris_str); } if (svga_have_vgpu10(svga)) { define_rasterizer_object(svga, rast); } if (templ->poly_smooth) { pipe_debug_message(&svga->debug.callback, CONFORMANCE, "GL_POLYGON_SMOOTH not supported"); } svga->hud.num_state_objects++; return rast; } static void svga_bind_rasterizer_state( struct pipe_context *pipe, void *state ) { struct svga_context *svga = svga_context(pipe); struct svga_rasterizer_state *raster = (struct svga_rasterizer_state *)state; if (!raster || !svga->curr.rast || raster->templ.poly_stipple_enable != svga->curr.rast->templ.poly_stipple_enable) { svga->dirty |= SVGA_NEW_STIPPLE; } svga->curr.rast = raster; svga->dirty |= SVGA_NEW_RAST; } static void svga_delete_rasterizer_state(struct pipe_context *pipe, void *state) { struct svga_context *svga = svga_context(pipe); struct svga_rasterizer_state *raster = (struct svga_rasterizer_state *) state; if (svga_have_vgpu10(svga)) { enum pipe_error ret = SVGA3D_vgpu10_DestroyRasterizerState(svga->swc, raster->id); if (ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_vgpu10_DestroyRasterizerState(svga->swc, raster->id); } if (raster->id == svga->state.hw_draw.rasterizer_id) svga->state.hw_draw.rasterizer_id = SVGA3D_INVALID_ID; util_bitmask_clear(svga->rast_object_id_bm, raster->id); } FREE(state); svga->hud.num_state_objects--; } void svga_init_rasterizer_functions( struct svga_context *svga ) { svga->pipe.create_rasterizer_state = svga_create_rasterizer_state; svga->pipe.bind_rasterizer_state = svga_bind_rasterizer_state; svga->pipe.delete_rasterizer_state = svga_delete_rasterizer_state; }
struct svga_stream_output * svga_create_stream_output(struct svga_context *svga, struct svga_shader *shader, const struct pipe_stream_output_info *info) { struct svga_stream_output *streamout; SVGA3dStreamOutputDeclarationEntry decls[SVGA3D_MAX_STREAMOUT_DECLS]; unsigned strides[SVGA3D_DX_MAX_SOTARGETS]; unsigned i; enum pipe_error ret; unsigned id; assert(info->num_outputs <= PIPE_MAX_SO_OUTPUTS); /* Gallium utility creates shaders with stream output. * For non-DX10, just return NULL. */ if (!svga_have_vgpu10(svga)) return NULL; assert(info->num_outputs <= SVGA3D_MAX_STREAMOUT_DECLS); /* Allocate an integer ID for the stream output */ id = util_bitmask_add(svga->stream_output_id_bm); if (id == UTIL_BITMASK_INVALID_INDEX) { return NULL; } /* Allocate the streamout data structure */ streamout = CALLOC_STRUCT(svga_stream_output); if (!streamout) return NULL; streamout->info = *info; streamout->id = id; streamout->pos_out_index = -1; SVGA_DBG(DEBUG_STREAMOUT, "%s, num_outputs=%d id=%d\n", __FUNCTION__, info->num_outputs, id); /* init whole decls and stride arrays to zero to avoid garbage values */ memset(decls, 0, sizeof(decls)); memset(strides, 0, sizeof(strides)); for (i = 0; i < info->num_outputs; i++) { unsigned reg_idx = info->output[i].register_index; unsigned buf_idx = info->output[i].output_buffer; const unsigned sem_name = shader->info.output_semantic_name[reg_idx]; assert(buf_idx <= PIPE_MAX_SO_BUFFERS); if (sem_name == TGSI_SEMANTIC_POSITION) { /** * Check if streaming out POSITION. If so, replace the * register index with the index for NON_ADJUSTED POSITION. */ decls[i].registerIndex = shader->info.num_outputs; /* Save this output index, so we can tell later if this stream output * includes an output of a vertex position */ streamout->pos_out_index = i; } else if (sem_name == TGSI_SEMANTIC_CLIPDIST) { /** * Use the shadow copy for clip distance because * CLIPDIST instruction is only emitted for enabled clip planes. * It's valid to write to ClipDistance variable for non-enabled * clip planes. */ decls[i].registerIndex = shader->info.num_outputs + 1 + shader->info.output_semantic_index[reg_idx]; } else { decls[i].registerIndex = reg_idx; } decls[i].outputSlot = buf_idx; decls[i].registerMask = ((1 << info->output[i].num_components) - 1) << info->output[i].start_component; SVGA_DBG(DEBUG_STREAMOUT, "%d slot=%d regIdx=%d regMask=0x%x\n", i, decls[i].outputSlot, decls[i].registerIndex, decls[i].registerMask); strides[buf_idx] = info->stride[buf_idx] * sizeof(float); } ret = SVGA3D_vgpu10_DefineStreamOutput(svga->swc, id, info->num_outputs, strides, decls); if (ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_vgpu10_DefineStreamOutput(svga->swc, id, info->num_outputs, strides, decls); if (ret != PIPE_OK) { util_bitmask_clear(svga->stream_output_id_bm, id); FREE(streamout); streamout = NULL; } } return streamout; }
/** * Create a DX ShaderResourceSamplerView for the given pipe_sampler_view, * if needed. */ enum pipe_error svga_validate_pipe_sampler_view(struct svga_context *svga, struct svga_pipe_sampler_view *sv) { enum pipe_error ret = PIPE_OK; if (sv->id == SVGA3D_INVALID_ID) { struct svga_screen *ss = svga_screen(svga->pipe.screen); struct pipe_resource *texture = sv->base.texture; struct svga_winsys_surface *surface = svga_resource_handle(texture); SVGA3dSurfaceFormat format; SVGA3dResourceType resourceDim; SVGA3dShaderResourceViewDesc viewDesc; enum pipe_format viewFormat = sv->base.format; /* vgpu10 cannot create a BGRX view for a BGRA resource, so force it to * create a BGRA view (and vice versa). */ if (viewFormat == PIPE_FORMAT_B8G8R8X8_UNORM && svga_texture_device_format_has_alpha(texture)) { viewFormat = PIPE_FORMAT_B8G8R8A8_UNORM; } else if (viewFormat == PIPE_FORMAT_B8G8R8A8_UNORM && !svga_texture_device_format_has_alpha(texture)) { viewFormat = PIPE_FORMAT_B8G8R8X8_UNORM; } format = svga_translate_format(ss, viewFormat, PIPE_BIND_SAMPLER_VIEW); assert(format != SVGA3D_FORMAT_INVALID); /* Convert the format to a sampler-friendly format, if needed */ format = svga_sampler_format(format); if (texture->target == PIPE_BUFFER) { unsigned elem_size = util_format_get_blocksize(sv->base.format); viewDesc.buffer.firstElement = sv->base.u.buf.offset / elem_size; viewDesc.buffer.numElements = sv->base.u.buf.size / elem_size; } else { viewDesc.tex.mostDetailedMip = sv->base.u.tex.first_level; viewDesc.tex.firstArraySlice = sv->base.u.tex.first_layer; viewDesc.tex.mipLevels = (sv->base.u.tex.last_level - sv->base.u.tex.first_level + 1); } /* arraySize in viewDesc specifies the number of array slices in a * texture array. For 3D texture, last_layer in * pipe_sampler_view specifies the last slice of the texture * which is different from the last slice in a texture array, * hence we need to set arraySize to 1 explicitly. */ viewDesc.tex.arraySize = (texture->target == PIPE_TEXTURE_3D || texture->target == PIPE_BUFFER) ? 1 : (sv->base.u.tex.last_layer - sv->base.u.tex.first_layer + 1); switch (texture->target) { case PIPE_BUFFER: resourceDim = SVGA3D_RESOURCE_BUFFER; break; case PIPE_TEXTURE_1D: case PIPE_TEXTURE_1D_ARRAY: resourceDim = SVGA3D_RESOURCE_TEXTURE1D; break; case PIPE_TEXTURE_RECT: case PIPE_TEXTURE_2D: case PIPE_TEXTURE_2D_ARRAY: resourceDim = SVGA3D_RESOURCE_TEXTURE2D; break; case PIPE_TEXTURE_3D: resourceDim = SVGA3D_RESOURCE_TEXTURE3D; break; case PIPE_TEXTURE_CUBE: case PIPE_TEXTURE_CUBE_ARRAY: resourceDim = SVGA3D_RESOURCE_TEXTURECUBE; break; default: assert(!"Unexpected texture type"); resourceDim = SVGA3D_RESOURCE_TEXTURE2D; } sv->id = util_bitmask_add(svga->sampler_view_id_bm); ret = SVGA3D_vgpu10_DefineShaderResourceView(svga->swc, sv->id, surface, format, resourceDim, &viewDesc); if (ret != PIPE_OK) { util_bitmask_clear(svga->sampler_view_id_bm, sv->id); sv->id = SVGA3D_INVALID_ID; } } return ret; }
/** * Define a vgpu10 sampler state. */ static void define_sampler_state_object(struct svga_context *svga, struct svga_sampler_state *ss, const struct pipe_sampler_state *ps) { uint8_t max_aniso = (uint8_t) 255; /* XXX fix me */ boolean anisotropic; uint8 compare_func; SVGA3dFilter filter; SVGA3dRGBAFloat bcolor; unsigned try; float min_lod, max_lod; assert(svga_have_vgpu10(svga)); anisotropic = ss->aniso_level > 1.0f; filter = translate_filter_mode(ps->min_mip_filter, ps->min_img_filter, ps->mag_img_filter, anisotropic, ss->compare_mode); compare_func = translate_comparison_func(ss->compare_func); COPY_4V(bcolor.value, ps->border_color.f); assert(ps->min_lod <= ps->max_lod); if (ps->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) { /* just use the base level image */ min_lod = max_lod = 0.0f; } else { min_lod = ps->min_lod; max_lod = ps->max_lod; } /* If shadow comparisons are enabled, create two sampler states: one * with the given shadow compare mode, another with shadow comparison off. * We need the later because in some cases, we have to do the shadow * compare in the shader. So, we don't want to do it twice. */ STATIC_ASSERT(PIPE_TEX_COMPARE_NONE == 0); STATIC_ASSERT(PIPE_TEX_COMPARE_R_TO_TEXTURE == 1); ss->id[1] = SVGA3D_INVALID_ID; unsigned i; for (i = 0; i <= ss->compare_mode; i++) { ss->id[i] = util_bitmask_add(svga->sampler_object_id_bm); /* Loop in case command buffer is full and we need to flush and retry */ for (try = 0; try < 2; try++) { enum pipe_error ret = SVGA3D_vgpu10_DefineSamplerState(svga->swc, ss->id[i], filter, ss->addressu, ss->addressv, ss->addressw, ss->lod_bias, /* float */ max_aniso, compare_func, bcolor, min_lod, /* float */ max_lod); /* float */ if (ret == PIPE_OK) break; svga_context_flush(svga, NULL); } /* turn off the shadow compare option for second iteration */ filter &= ~SVGA3D_FILTER_COMPARE; } } static void * svga_create_sampler_state(struct pipe_context *pipe, const struct pipe_sampler_state *sampler) { struct svga_context *svga = svga_context(pipe); struct svga_sampler_state *cso = CALLOC_STRUCT( svga_sampler_state ); if (!cso) return NULL; cso->mipfilter = translate_mip_filter(sampler->min_mip_filter); cso->magfilter = translate_img_filter( sampler->mag_img_filter ); cso->minfilter = translate_img_filter( sampler->min_img_filter ); cso->aniso_level = MAX2( sampler->max_anisotropy, 1 ); if (sampler->max_anisotropy) cso->magfilter = cso->minfilter = SVGA3D_TEX_FILTER_ANISOTROPIC; cso->lod_bias = sampler->lod_bias; cso->addressu = translate_wrap_mode(sampler->wrap_s); cso->addressv = translate_wrap_mode(sampler->wrap_t); cso->addressw = translate_wrap_mode(sampler->wrap_r); cso->normalized_coords = sampler->normalized_coords; cso->compare_mode = sampler->compare_mode; cso->compare_func = sampler->compare_func; { uint32 r = float_to_ubyte(sampler->border_color.f[0]); uint32 g = float_to_ubyte(sampler->border_color.f[1]); uint32 b = float_to_ubyte(sampler->border_color.f[2]); uint32 a = float_to_ubyte(sampler->border_color.f[3]); cso->bordercolor = (a << 24) | (r << 16) | (g << 8) | b; } /* No SVGA3D support for: * - min/max LOD clamping */ cso->min_lod = 0; cso->view_min_lod = MAX2((int) (sampler->min_lod + 0.5), 0); cso->view_max_lod = MAX2((int) (sampler->max_lod + 0.5), 0); /* Use min_mipmap */ if (svga->debug.use_min_mipmap) { if (cso->view_min_lod == cso->view_max_lod) { cso->min_lod = cso->view_min_lod; cso->view_min_lod = 0; cso->view_max_lod = 1000; /* Just a high number */ cso->mipfilter = SVGA3D_TEX_FILTER_NONE; } } if (svga_have_vgpu10(svga)) { define_sampler_state_object(svga, cso, sampler); } SVGA_DBG(DEBUG_SAMPLERS, "New sampler: min %u, view(min %u, max %u) lod, mipfilter %s\n", cso->min_lod, cso->view_min_lod, cso->view_max_lod, cso->mipfilter == SVGA3D_TEX_FILTER_NONE ? "SVGA3D_TEX_FILTER_NONE" : "SOMETHING"); svga->hud.num_sampler_objects++; SVGA_STATS_COUNT_INC(svga_screen(svga->pipe.screen)->sws, SVGA_STATS_COUNT_SAMPLER); return cso; } static void svga_bind_sampler_states(struct pipe_context *pipe, enum pipe_shader_type shader, unsigned start, unsigned num, void **samplers) { struct svga_context *svga = svga_context(pipe); unsigned i; boolean any_change = FALSE; assert(shader < PIPE_SHADER_TYPES); assert(start + num <= PIPE_MAX_SAMPLERS); /* Pre-VGPU10 only supports FS textures */ if (!svga_have_vgpu10(svga) && shader != PIPE_SHADER_FRAGMENT) return; for (i = 0; i < num; i++) { if (svga->curr.sampler[shader][start + i] != samplers[i]) any_change = TRUE; svga->curr.sampler[shader][start + i] = samplers[i]; } if (!any_change) { return; } /* find highest non-null sampler[] entry */ { unsigned j = MAX2(svga->curr.num_samplers[shader], start + num); while (j > 0 && svga->curr.sampler[shader][j - 1] == NULL) j--; svga->curr.num_samplers[shader] = j; } svga->dirty |= SVGA_NEW_SAMPLER; } static void svga_delete_sampler_state(struct pipe_context *pipe, void *sampler) { struct svga_sampler_state *ss = (struct svga_sampler_state *) sampler; struct svga_context *svga = svga_context(pipe); if (svga_have_vgpu10(svga)) { unsigned i; for (i = 0; i < 2; i++) { enum pipe_error ret; if (ss->id[i] != SVGA3D_INVALID_ID) { svga_hwtnl_flush_retry(svga); ret = SVGA3D_vgpu10_DestroySamplerState(svga->swc, ss->id[i]); if (ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_vgpu10_DestroySamplerState(svga->swc, ss->id[i]); } util_bitmask_clear(svga->sampler_object_id_bm, ss->id[i]); } } } FREE(sampler); svga->hud.num_sampler_objects--; } static struct pipe_sampler_view * svga_create_sampler_view(struct pipe_context *pipe, struct pipe_resource *texture, const struct pipe_sampler_view *templ) { struct svga_context *svga = svga_context(pipe); struct svga_pipe_sampler_view *sv = CALLOC_STRUCT(svga_pipe_sampler_view); if (!sv) { return NULL; } sv->base = *templ; sv->base.reference.count = 1; sv->base.texture = NULL; pipe_resource_reference(&sv->base.texture, texture); sv->base.context = pipe; sv->id = SVGA3D_INVALID_ID; svga->hud.num_samplerview_objects++; SVGA_STATS_COUNT_INC(svga_screen(svga->pipe.screen)->sws, SVGA_STATS_COUNT_SAMPLERVIEW); return &sv->base; } static void svga_sampler_view_destroy(struct pipe_context *pipe, struct pipe_sampler_view *view) { struct svga_context *svga = svga_context(pipe); struct svga_pipe_sampler_view *sv = svga_pipe_sampler_view(view); if (svga_have_vgpu10(svga) && sv->id != SVGA3D_INVALID_ID) { if (view->context != pipe) { /* The SVGA3D device will generate an error (and on Linux, cause * us to abort) if we try to destroy a shader resource view from * a context other than the one it was created with. Skip the * SVGA3D_vgpu10_DestroyShaderResourceView() and leak the sampler * view for now. This should only sometimes happen when a shared * texture is deleted. */ _debug_printf("context mismatch in %s\n", __func__); } else { enum pipe_error ret; svga_hwtnl_flush_retry(svga); /* XXX is this needed? */ ret = SVGA3D_vgpu10_DestroyShaderResourceView(svga->swc, sv->id); if (ret != PIPE_OK) { svga_context_flush(svga, NULL); ret = SVGA3D_vgpu10_DestroyShaderResourceView(svga->swc, sv->id); } util_bitmask_clear(svga->sampler_view_id_bm, sv->id); } } pipe_resource_reference(&sv->base.texture, NULL); FREE(sv); svga->hud.num_samplerview_objects--; } static void svga_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader, unsigned start, unsigned num, struct pipe_sampler_view **views) { struct svga_context *svga = svga_context(pipe); unsigned flag_1d = 0; unsigned flag_srgb = 0; uint i; boolean any_change = FALSE; assert(shader < PIPE_SHADER_TYPES); assert(start + num <= ARRAY_SIZE(svga->curr.sampler_views[shader])); /* Pre-VGPU10 only supports FS textures */ if (!svga_have_vgpu10(svga) && shader != PIPE_SHADER_FRAGMENT) return; SVGA_STATS_TIME_PUSH(svga_sws(svga), SVGA_STATS_TIME_SETSAMPLERVIEWS); /* This bit of code works around a quirk in the CSO module. * If start=num=0 it means all sampler views should be released. * Note that the CSO module treats sampler views for fragment shaders * differently than other shader types. */ if (start == 0 && num == 0 && svga->curr.num_sampler_views[shader] > 0) { for (i = 0; i < svga->curr.num_sampler_views[shader]; i++) { pipe_sampler_view_release(pipe, &svga->curr.sampler_views[shader][i]); } any_change = TRUE; } for (i = 0; i < num; i++) { enum pipe_texture_target target; if (svga->curr.sampler_views[shader][start + i] != views[i]) { /* Note: we're using pipe_sampler_view_release() here to work around * a possible crash when the old view belongs to another context that * was already destroyed. */ pipe_sampler_view_release(pipe, &svga->curr.sampler_views[shader][start + i]); pipe_sampler_view_reference(&svga->curr.sampler_views[shader][start + i], views[i]); any_change = TRUE; } if (!views[i]) continue; if (util_format_is_srgb(views[i]->format)) flag_srgb |= 1 << (start + i); target = views[i]->target; if (target == PIPE_TEXTURE_1D) { flag_1d |= 1 << (start + i); } else if (target == PIPE_TEXTURE_RECT) { /* If the size of the bound texture changes, we need to emit new * const buffer values. */ svga->dirty |= SVGA_NEW_TEXTURE_CONSTS; } else if (target == PIPE_BUFFER) { /* If the size of the bound buffer changes, we need to emit new * const buffer values. */ svga->dirty |= SVGA_NEW_TEXTURE_CONSTS; } } if (!any_change) { goto done; } /* find highest non-null sampler_views[] entry */ { unsigned j = MAX2(svga->curr.num_sampler_views[shader], start + num); while (j > 0 && svga->curr.sampler_views[shader][j - 1] == NULL) j--; svga->curr.num_sampler_views[shader] = j; } svga->dirty |= SVGA_NEW_TEXTURE_BINDING; if (flag_srgb != svga->curr.tex_flags.flag_srgb || flag_1d != svga->curr.tex_flags.flag_1d) { svga->dirty |= SVGA_NEW_TEXTURE_FLAGS; svga->curr.tex_flags.flag_1d = flag_1d; svga->curr.tex_flags.flag_srgb = flag_srgb; } /* Check if any of the sampler view resources collide with the framebuffer * color buffers or depth stencil resource. If so, set the NEW_FRAME_BUFFER * dirty bit so that emit_framebuffer can be invoked to create backed view * for the conflicted surface view. */ if (svga_check_sampler_framebuffer_resource_collision(svga, shader)) { svga->dirty |= SVGA_NEW_FRAME_BUFFER; } done: SVGA_STATS_TIME_POP(svga_sws(svga)); } /** * Clean up sampler, sampler view state at context destruction time */ void svga_cleanup_sampler_state(struct svga_context *svga) { enum pipe_shader_type shader; for (shader = 0; shader <= PIPE_SHADER_GEOMETRY; shader++) { unsigned i; for (i = 0; i < svga->state.hw_draw.num_sampler_views[shader]; i++) { pipe_sampler_view_release(&svga->pipe, &svga->state.hw_draw.sampler_views[shader][i]); } } /* free polygon stipple state */ if (svga->polygon_stipple.sampler) { svga->pipe.delete_sampler_state(&svga->pipe, svga->polygon_stipple.sampler); } if (svga->polygon_stipple.sampler_view) { svga->pipe.sampler_view_destroy(&svga->pipe, &svga->polygon_stipple.sampler_view->base); } pipe_resource_reference(&svga->polygon_stipple.texture, NULL); } void svga_init_sampler_functions( struct svga_context *svga ) { svga->pipe.create_sampler_state = svga_create_sampler_state; svga->pipe.bind_sampler_states = svga_bind_sampler_states; svga->pipe.delete_sampler_state = svga_delete_sampler_state; svga->pipe.set_sampler_views = svga_set_sampler_views; svga->pipe.create_sampler_view = svga_create_sampler_view; svga->pipe.sampler_view_destroy = svga_sampler_view_destroy; }
static void svga_surface_destroy(struct pipe_context *pipe, struct pipe_surface *surf) { struct svga_context *svga = svga_context(pipe); struct svga_surface *s = svga_surface(surf); struct svga_texture *t = svga_texture(surf->texture); struct svga_screen *ss = svga_screen(surf->texture->screen); enum pipe_error ret = PIPE_OK; /* Destroy the backed view surface if it exists */ if (s->backed) { svga_surface_destroy(pipe, &s->backed->base); s->backed = NULL; } if (s->handle != t->handle) { SVGA_DBG(DEBUG_DMA, "unref sid %p (tex surface)\n", s->handle); svga_screen_surface_destroy(ss, &s->key, &s->handle); } if (s->view_id != SVGA3D_INVALID_ID) { unsigned try; assert(svga_have_vgpu10(svga)); for (try = 0; try < 2; try++) { if (util_format_is_depth_or_stencil(s->base.format)) { ret = SVGA3D_vgpu10_DestroyDepthStencilView(svga->swc, s->view_id); } else { ret = SVGA3D_vgpu10_DestroyRenderTargetView(svga->swc, s->view_id); } if (ret == PIPE_OK) break; svga_context_flush(svga, NULL); } assert(ret == PIPE_OK); util_bitmask_clear(svga->surface_view_id_bm, s->view_id); } pipe_resource_reference(&surf->texture, NULL); FREE(surf); svga->hud.num_surface_views--; } static void svga_mark_surface_dirty(struct pipe_surface *surf) { struct svga_surface *s = svga_surface(surf); struct svga_texture *tex = svga_texture(surf->texture); if (!s->dirty) { s->dirty = TRUE; if (s->handle == tex->handle) { /* hmm so 3d textures always have all their slices marked ? */ svga_define_texture_level(tex, surf->u.tex.first_layer, surf->u.tex.level); } else { /* this will happen later in svga_propagate_surface */ } } /* Increment the view_age and texture age for this surface's mipmap * level so that any sampler views into the texture are re-validated too. */ svga_age_texture_view(tex, surf->u.tex.level); } void svga_mark_surfaces_dirty(struct svga_context *svga) { struct svga_screen *svgascreen = svga_screen(svga->pipe.screen); unsigned i; for (i = 0; i < svgascreen->max_color_buffers; i++) { if (svga->curr.framebuffer.cbufs[i]) svga_mark_surface_dirty(svga->curr.framebuffer.cbufs[i]); } if (svga->curr.framebuffer.zsbuf) svga_mark_surface_dirty(svga->curr.framebuffer.zsbuf); } /** * Progagate any changes from surfaces to texture. * pipe is optional context to inline the blit command in. */ void svga_propagate_surface(struct svga_context *svga, struct pipe_surface *surf) { struct svga_surface *s = svga_surface(surf); struct svga_texture *tex = svga_texture(surf->texture); struct svga_screen *ss = svga_screen(surf->texture->screen); unsigned zslice, layer; unsigned nlayers = 1; unsigned i; if (!s->dirty) return; if (surf->texture->target == PIPE_TEXTURE_CUBE) { zslice = 0; layer = surf->u.tex.first_layer; } else if (surf->texture->target == PIPE_TEXTURE_1D_ARRAY || surf->texture->target == PIPE_TEXTURE_2D_ARRAY) { zslice = 0; layer = surf->u.tex.first_layer; nlayers = surf->u.tex.last_layer - surf->u.tex.first_layer + 1; } else { zslice = surf->u.tex.first_layer; layer = 0; } s->dirty = FALSE; ss->texture_timestamp++; svga_age_texture_view(tex, surf->u.tex.level); if (s->handle != tex->handle) { SVGA_DBG(DEBUG_VIEWS, "svga: Surface propagate: tex %p, level %u, from %p\n", tex, surf->u.tex.level, surf); for (i = 0; i < nlayers; i++) { svga_texture_copy_handle(svga, s->handle, 0, 0, 0, s->real_level, s->real_layer + i, tex->handle, 0, 0, zslice, surf->u.tex.level, layer + i, u_minify(tex->b.b.width0, surf->u.tex.level), u_minify(tex->b.b.height0, surf->u.tex.level), 1); svga_define_texture_level(tex, layer + i, surf->u.tex.level); } } } /** * Check if we should call svga_propagate_surface on the surface. */ boolean svga_surface_needs_propagation(const struct pipe_surface *surf) { const struct svga_surface *s = svga_surface_const(surf); struct svga_texture *tex = svga_texture(surf->texture); return s->dirty && s->handle != tex->handle; } static void svga_get_sample_position(struct pipe_context *context, unsigned sample_count, unsigned sample_index, float *pos_out) { /* We can't actually query the device to learn the sample positions. * These were grabbed from nvidia's driver. */ static const float pos1[1][2] = { { 0.5, 0.5 } }; static const float pos4[4][2] = { { 0.375000, 0.125000 }, { 0.875000, 0.375000 }, { 0.125000, 0.625000 }, { 0.625000, 0.875000 } }; static const float pos8[8][2] = { { 0.562500, 0.312500 }, { 0.437500, 0.687500 }, { 0.812500, 0.562500 }, { 0.312500, 0.187500 }, { 0.187500, 0.812500 }, { 0.062500, 0.437500 }, { 0.687500, 0.937500 }, { 0.937500, 0.062500 } }; static const float pos16[16][2] = { { 0.187500, 0.062500 }, { 0.437500, 0.187500 }, { 0.062500, 0.312500 }, { 0.312500, 0.437500 }, { 0.687500, 0.062500 }, { 0.937500, 0.187500 }, { 0.562500, 0.312500 }, { 0.812500, 0.437500 }, { 0.187500, 0.562500 }, { 0.437500, 0.687500 }, { 0.062500, 0.812500 }, { 0.312500, 0.937500 }, { 0.687500, 0.562500 }, { 0.937500, 0.687500 }, { 0.562500, 0.812500 }, { 0.812500, 0.937500 } }; const float (*positions)[2]; switch (sample_count) { case 4: positions = pos4; break; case 8: positions = pos8; break; case 16: positions = pos16; break; default: positions = pos1; } pos_out[0] = positions[sample_index][0]; pos_out[1] = positions[sample_index][1]; } void svga_init_surface_functions(struct svga_context *svga) { svga->pipe.create_surface = svga_create_surface; svga->pipe.surface_destroy = svga_surface_destroy; svga->pipe.get_sample_position = svga_get_sample_position; }
/** * Create a DX RenderTarget/DepthStencil View for the given surface, * if needed. */ struct pipe_surface * svga_validate_surface_view(struct svga_context *svga, struct svga_surface *s) { enum pipe_error ret = PIPE_OK; unsigned shader; assert(svga_have_vgpu10(svga)); /** * DX spec explicitly specifies that no resource can be bound to a render * target view and a shader resource view simultanously. * So first check if the resource bound to this surface view collides with * a sampler view. If so, then we will clone this surface view and its * associated resource. We will then use the cloned surface view for * render target. */ for (shader = PIPE_SHADER_VERTEX; shader <= PIPE_SHADER_GEOMETRY; shader++) { if (svga_check_sampler_view_resource_collision(svga, s->handle, shader)) { SVGA_DBG(DEBUG_VIEWS, "same resource used in shaderResource and renderTarget 0x%x\n", s->handle); s = create_backed_surface_view(svga, s); if (!s) return NULL; break; } } if (s->view_id == SVGA3D_INVALID_ID) { SVGA3dResourceType resType; SVGA3dRenderTargetViewDesc desc; desc.tex.mipSlice = s->real_level; desc.tex.firstArraySlice = s->real_layer + s->real_zslice; desc.tex.arraySize = s->base.u.tex.last_layer - s->base.u.tex.first_layer + 1; s->view_id = util_bitmask_add(svga->surface_view_id_bm); switch (s->base.texture->target) { case PIPE_TEXTURE_1D: case PIPE_TEXTURE_1D_ARRAY: resType = SVGA3D_RESOURCE_TEXTURE1D; break; case PIPE_TEXTURE_RECT: case PIPE_TEXTURE_2D: case PIPE_TEXTURE_2D_ARRAY: case PIPE_TEXTURE_CUBE: /* drawing to cube map is treated as drawing to 2D array */ resType = SVGA3D_RESOURCE_TEXTURE2D; break; case PIPE_TEXTURE_3D: resType = SVGA3D_RESOURCE_TEXTURE3D; break; default: assert(!"Unexpected texture target"); resType = SVGA3D_RESOURCE_TEXTURE2D; } if (util_format_is_depth_or_stencil(s->base.format)) { ret = SVGA3D_vgpu10_DefineDepthStencilView(svga->swc, s->view_id, s->handle, s->key.format, resType, &desc); } else { ret = SVGA3D_vgpu10_DefineRenderTargetView(svga->swc, s->view_id, s->handle, s->key.format, resType, &desc); } if (ret != PIPE_OK) { util_bitmask_clear(svga->surface_view_id_bm, s->view_id); s->view_id = SVGA3D_INVALID_ID; return NULL; } } return &s->base; }