struct pipe_context *
fd_context_init(struct fd_context *ctx, struct pipe_screen *pscreen,
const uint8_t *primtypes, void *priv)
{
struct fd_screen *screen = fd_screen(pscreen);
struct pipe_context *pctx;
int i;
ctx->screen = screen;
ctx->primtypes = primtypes;
ctx->primtype_mask = 0;
for (i = 0; i < PIPE_PRIM_MAX; i++)
if (primtypes[i])
ctx->primtype_mask |= (1 << i);
/* need some sane default in case state tracker doesn't
* set some state:
*/
ctx->sample_mask = 0xffff;
pctx = &ctx->base;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->flush = fd_context_flush;
for (i = 0; i < ARRAY_SIZE(ctx->rings); i++) {
ctx->rings[i] = fd_ringbuffer_new(screen->pipe, 0x100000);
if (!ctx->rings[i])
goto fail;
}
fd_context_next_rb(pctx);
fd_reset_wfi(ctx);
util_dynarray_init(&ctx->draw_patches);
util_slab_create(&ctx->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
fd_draw_init(pctx);
fd_resource_context_init(pctx);
fd_query_context_init(pctx);
fd_texture_init(pctx);
fd_state_init(pctx);
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter)
goto fail;
ctx->primconvert = util_primconvert_create(pctx, ctx->primtype_mask);
if (!ctx->primconvert)
goto fail;
return pctx;
fail:
pctx->destroy(pctx);
return NULL;
}
boolean svga_init_swtnl( struct svga_context *svga )
{
struct svga_screen *screen = svga_screen(svga->pipe.screen);
svga->swtnl.backend = svga_vbuf_render_create(svga);
if(!svga->swtnl.backend)
goto fail;
/*
* Create drawing context and plug our rendering stage into it.
*/
svga->swtnl.draw = draw_create(&svga->pipe);
if (svga->swtnl.draw == NULL)
goto fail;
draw_set_rasterize_stage(svga->swtnl.draw,
draw_vbuf_stage( svga->swtnl.draw, svga->swtnl.backend ));
draw_set_render(svga->swtnl.draw, svga->swtnl.backend);
svga->blitter = util_blitter_create(&svga->pipe);
if (!svga->blitter)
goto fail;
/* must be done before installing Draw stages */
util_blitter_cache_all_shaders(svga->blitter);
if (!screen->haveLineSmooth)
draw_install_aaline_stage(svga->swtnl.draw, &svga->pipe);
/* enable/disable line stipple stage depending on device caps */
draw_enable_line_stipple(svga->swtnl.draw, !screen->haveLineStipple);
/* always install AA point stage */
draw_install_aapoint_stage(svga->swtnl.draw, &svga->pipe);
/* Set wide line threshold above device limit (so we'll never really use it)
*/
draw_wide_line_threshold(svga->swtnl.draw,
MAX2(screen->maxLineWidth,
screen->maxLineWidthAA));
if (debug_get_bool_option("SVGA_SWTNL_FSE", FALSE))
draw_set_driver_clipping(svga->swtnl.draw, TRUE, TRUE, TRUE, FALSE);
return TRUE;
fail:
if (svga->blitter)
util_blitter_destroy(svga->blitter);
if (svga->swtnl.backend)
svga->swtnl.backend->destroy( svga->swtnl.backend );
if (svga->swtnl.draw)
draw_destroy( svga->swtnl.draw );
return FALSE;
}
struct pipe_context *
vc4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
{
struct vc4_screen *screen = vc4_screen(pscreen);
struct vc4_context *vc4;
/* Prevent dumping of the shaders built during context setup. */
uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
vc4_debug &= ~VC4_DEBUG_SHADERDB;
vc4 = rzalloc(NULL, struct vc4_context);
if (!vc4)
return NULL;
struct pipe_context *pctx = &vc4->base;
vc4->screen = screen;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->destroy = vc4_context_destroy;
pctx->flush = vc4_pipe_flush;
pctx->invalidate_resource = vc4_invalidate_resource;
vc4_draw_init(pctx);
vc4_state_init(pctx);
vc4_program_init(pctx);
vc4_query_init(pctx);
vc4_resource_context_init(pctx);
vc4_job_init(vc4);
vc4->fd = screen->fd;
util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
16, UTIL_SLAB_SINGLETHREADED);
vc4->blitter = util_blitter_create(pctx);
if (!vc4->blitter)
goto fail;
vc4->primconvert = util_primconvert_create(pctx,
(1 << PIPE_PRIM_QUADS) - 1);
if (!vc4->primconvert)
goto fail;
vc4->uploader = u_upload_create(pctx, 16 * 1024,
PIPE_BIND_INDEX_BUFFER,
PIPE_USAGE_STREAM);
vc4_debug |= saved_shaderdb_flag;
vc4->sample_mask = (1 << VC4_MAX_SAMPLES) - 1;
return &vc4->base;
fail:
pctx->destroy(pctx);
return NULL;
}
struct pipe_context *
swr_create_context(struct pipe_screen *p_screen, void *priv, unsigned flags)
{
struct swr_context *ctx = CALLOC_STRUCT(swr_context);
ctx->blendJIT =
new std::unordered_map<BLEND_COMPILE_STATE, PFN_BLEND_JIT_FUNC>;
SWR_CREATECONTEXT_INFO createInfo;
createInfo.driver = GL;
createInfo.privateStateSize = sizeof(swr_draw_context);
createInfo.pfnLoadTile = swr_LoadHotTile;
createInfo.pfnStoreTile = swr_StoreHotTile;
createInfo.pfnClearTile = swr_StoreHotTileClear;
ctx->swrContext = SwrCreateContext(&createInfo);
/* Init Load/Store/ClearTiles Tables */
swr_InitMemoryModule();
InitBackendFuncTables();
if (ctx->swrContext == NULL)
goto fail;
ctx->pipe.screen = p_screen;
ctx->pipe.destroy = swr_destroy;
ctx->pipe.priv = priv;
ctx->pipe.create_surface = swr_create_surface;
ctx->pipe.surface_destroy = swr_surface_destroy;
ctx->pipe.transfer_map = swr_transfer_map;
ctx->pipe.transfer_unmap = swr_transfer_unmap;
ctx->pipe.transfer_flush_region = u_default_transfer_flush_region;
ctx->pipe.buffer_subdata = u_default_buffer_subdata;
ctx->pipe.texture_subdata = u_default_texture_subdata;
ctx->pipe.resource_copy_region = swr_resource_copy;
ctx->pipe.render_condition = swr_render_condition;
swr_state_init(&ctx->pipe);
swr_clear_init(&ctx->pipe);
swr_draw_init(&ctx->pipe);
swr_query_init(&ctx->pipe);
ctx->pipe.blit = swr_blit;
ctx->blitter = util_blitter_create(&ctx->pipe);
if (!ctx->blitter)
goto fail;
swr_init_scratch_buffers(ctx);
return &ctx->pipe;
fail:
/* Should really validate the init steps and fail gracefully */
swr_destroy(&ctx->pipe);
return NULL;
}
static bool
ilo_blitter_pipe_create(struct ilo_blitter *blitter)
{
if (blitter->pipe_blitter)
return true;
blitter->pipe_blitter = util_blitter_create(&blitter->ilo->base);
return (blitter->pipe_blitter != NULL);
}
struct pipe_context *
vc4_context_create(struct pipe_screen *pscreen, void *priv)
{
struct vc4_screen *screen = vc4_screen(pscreen);
struct vc4_context *vc4;
/* Prevent dumping of the shaders built during context setup. */
uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
vc4_debug &= ~VC4_DEBUG_SHADERDB;
vc4 = rzalloc(NULL, struct vc4_context);
if (vc4 == NULL)
return NULL;
struct pipe_context *pctx = &vc4->base;
vc4->screen = screen;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->destroy = vc4_context_destroy;
pctx->flush = vc4_pipe_flush;
vc4_draw_init(pctx);
vc4_state_init(pctx);
vc4_program_init(pctx);
vc4_query_init(pctx);
vc4_resource_context_init(pctx);
vc4_init_cl(vc4, &vc4->bcl);
vc4_init_cl(vc4, &vc4->rcl);
vc4_init_cl(vc4, &vc4->shader_rec);
vc4_init_cl(vc4, &vc4->bo_handles);
vc4->dirty = ~0;
vc4->fd = screen->fd;
util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
16, UTIL_SLAB_SINGLETHREADED);
vc4->blitter = util_blitter_create(pctx);
if (!vc4->blitter)
goto fail;
vc4->primconvert = util_primconvert_create(pctx,
(1 << PIPE_PRIM_QUADS) - 1);
if (!vc4->primconvert)
goto fail;
vc4_debug |= saved_shaderdb_flag;
return &vc4->base;
fail:
pctx->destroy(pctx);
return NULL;
}
struct pipe_context *
fd_context_create(struct pipe_screen *pscreen, void *priv)
{
struct fd_screen *screen = fd_screen(pscreen);
struct fd_context *ctx = CALLOC_STRUCT(fd_context);
struct pipe_context *pctx;
if (!ctx)
return NULL;
DBG("");
ctx->screen = screen;
ctx->ring = fd_ringbuffer_new(screen->pipe, 0x100000);
ctx->draw_start = fd_ringmarker_new(ctx->ring);
ctx->draw_end = fd_ringmarker_new(ctx->ring);
pctx = &ctx->base;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->flush = fd_context_flush;
pctx->destroy = fd_context_destroy;
util_slab_create(&ctx->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
fd_vbo_init(pctx);
fd_blend_init(pctx);
fd_rasterizer_init(pctx);
fd_zsa_init(pctx);
fd_state_init(pctx);
fd_resource_context_init(pctx);
fd_clear_init(pctx);
fd_prog_init(pctx);
fd_texture_init(pctx);
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter) {
fd_context_destroy(pctx);
return NULL;
}
/* construct vertex state used for solid ops (clear, and gmem<->mem) */
ctx->solid_vertexbuf = create_solid_vertexbuf(pctx);
fd_state_emit_setup(pctx);
return pctx;
}
boolean svga_init_swtnl( struct svga_context *svga )
{
svga->swtnl.backend = svga_vbuf_render_create(svga);
if(!svga->swtnl.backend)
goto fail;
/*
* Create drawing context and plug our rendering stage into it.
*/
svga->swtnl.draw = draw_create(&svga->pipe);
if (svga->swtnl.draw == NULL)
goto fail;
draw_set_rasterize_stage(svga->swtnl.draw,
draw_vbuf_stage( svga->swtnl.draw, svga->swtnl.backend ));
draw_set_render(svga->swtnl.draw, svga->swtnl.backend);
svga->blitter = util_blitter_create(&svga->pipe);
if (!svga->blitter)
goto fail;
/* must be done before installing Draw stages */
util_blitter_cache_all_shaders(svga->blitter);
draw_install_aaline_stage(svga->swtnl.draw, &svga->pipe);
draw_install_aapoint_stage(svga->swtnl.draw, &svga->pipe);
draw_install_pstipple_stage(svga->swtnl.draw, &svga->pipe);
if (debug_get_bool_option("SVGA_SWTNL_FSE", FALSE))
draw_set_driver_clipping(svga->swtnl.draw, TRUE, TRUE, TRUE);
return TRUE;
fail:
if (svga->blitter)
util_blitter_destroy(svga->blitter);
if (svga->swtnl.backend)
svga->swtnl.backend->destroy( svga->swtnl.backend );
if (svga->swtnl.draw)
draw_destroy( svga->swtnl.draw );
return FALSE;
}
struct pipe_context *
fd_context_init(struct fd_context *ctx,
struct pipe_screen *pscreen, void *priv)
{
struct fd_screen *screen = fd_screen(pscreen);
struct pipe_context *pctx;
ctx->screen = screen;
/* need some sane default in case state tracker doesn't
* set some state:
*/
ctx->sample_mask = 0xffff;
pctx = &ctx->base;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->flush = fd_context_flush;
ctx->ring = fd_ringbuffer_new(screen->pipe, 0x100000);
if (!ctx->ring)
goto fail;
ctx->draw_start = fd_ringmarker_new(ctx->ring);
ctx->draw_end = fd_ringmarker_new(ctx->ring);
util_slab_create(&ctx->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
fd_draw_init(pctx);
fd_resource_context_init(pctx);
fd_texture_init(pctx);
fd_state_init(pctx);
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter)
goto fail;
return pctx;
fail:
pctx->destroy(pctx);
return NULL;
}
struct pipe_context *
i915_create_context(struct pipe_screen *screen, void *priv)
{
struct i915_context *i915;
i915 = CALLOC_STRUCT(i915_context);
if (i915 == NULL)
return NULL;
i915->iws = i915_screen(screen)->iws;
i915->base.screen = screen;
i915->base.priv = priv;
i915->base.destroy = i915_destroy;
if (i915_screen(screen)->debug.use_blitter)
i915->base.clear = i915_clear_blitter;
else
i915->base.clear = i915_clear_render;
i915->base.draw_vbo = i915_draw_vbo;
/* init this before draw */
util_slab_create(&i915->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
util_slab_create(&i915->texture_transfer_pool, sizeof(struct i915_transfer),
16, UTIL_SLAB_SINGLETHREADED);
/* Batch stream debugging is a bit hacked up at the moment:
*/
i915->batch = i915->iws->batchbuffer_create(i915->iws);
/*
* Create drawing context and plug our rendering stage into it.
*/
i915->draw = draw_create(&i915->base);
assert(i915->draw);
if (!debug_get_option_i915_no_vbuf()) {
draw_set_rasterize_stage(i915->draw, i915_draw_vbuf_stage(i915));
} else {
draw_set_rasterize_stage(i915->draw, i915_draw_render_stage(i915));
}
i915_init_surface_functions(i915);
i915_init_state_functions(i915);
i915_init_flush_functions(i915);
i915_init_resource_functions(i915);
i915_init_query_functions(i915);
draw_install_aaline_stage(i915->draw, &i915->base);
draw_install_aapoint_stage(i915->draw, &i915->base);
draw_enable_point_sprites(i915->draw, TRUE);
/* augmented draw pipeline clobbers state functions */
i915_init_fixup_state_functions(i915);
/* Create blitter last - calls state creation functions. */
i915->blitter = util_blitter_create(&i915->base);
assert(i915->blitter);
i915->dirty = ~0;
i915->hardware_dirty = ~0;
i915->immediate_dirty = ~0;
i915->dynamic_dirty = ~0;
i915->static_dirty = ~0;
i915->flush_dirty = 0;
return &i915->base;
}
static struct pipe_context *r600_create_context(struct pipe_screen *screen,
void *priv, unsigned flags)
{
struct r600_context *rctx = CALLOC_STRUCT(r600_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
struct radeon_winsys *ws = rscreen->b.ws;
if (!rctx)
return NULL;
rctx->b.b.screen = screen;
assert(!priv);
rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
rctx->b.b.destroy = r600_destroy_context;
rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
goto fail;
rctx->screen = rscreen;
LIST_INITHEAD(&rctx->texture_buffers);
r600_init_blit_functions(rctx);
if (rscreen->b.info.has_hw_decode) {
rctx->b.b.create_video_codec = r600_uvd_create_decoder;
rctx->b.b.create_video_buffer = r600_video_buffer_create;
} else {
rctx->b.b.create_video_codec = vl_create_decoder;
rctx->b.b.create_video_buffer = vl_video_buffer_create;
}
if (getenv("R600_TRACE"))
rctx->is_debug = true;
r600_init_common_state_functions(rctx);
switch (rctx->b.chip_class) {
case R600:
case R700:
r600_init_state_functions(rctx);
r600_init_atom_start_cs(rctx);
rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
: r600_create_resolve_blend(rctx);
rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
rctx->b.family == CHIP_RV620 ||
rctx->b.family == CHIP_RS780 ||
rctx->b.family == CHIP_RS880 ||
rctx->b.family == CHIP_RV710);
break;
case EVERGREEN:
case CAYMAN:
evergreen_init_state_functions(rctx);
evergreen_init_atom_start_cs(rctx);
evergreen_init_atom_start_compute_cs(rctx);
rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
rctx->b.family == CHIP_PALM ||
rctx->b.family == CHIP_SUMO ||
rctx->b.family == CHIP_SUMO2 ||
rctx->b.family == CHIP_CAICOS ||
rctx->b.family == CHIP_CAYMAN ||
rctx->b.family == CHIP_ARUBA);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
goto fail;
}
rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
r600_context_gfx_flush, rctx);
rctx->b.gfx.flush = r600_context_gfx_flush;
rctx->allocator_fetch_shader =
u_suballocator_create(&rctx->b.b, 64 * 1024,
0, PIPE_USAGE_DEFAULT, 0, FALSE);
if (!rctx->allocator_fetch_shader)
goto fail;
rctx->isa = calloc(1, sizeof(struct r600_isa));
if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
goto fail;
if (rscreen->b.debug_flags & DBG_FORCE_DMA)
rctx->b.b.resource_copy_region = rctx->b.dma_copy;
rctx->blitter = util_blitter_create(&rctx->b.b);
if (rctx->blitter == NULL)
goto fail;
util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
rctx->blitter->draw_rectangle = r600_draw_rectangle;
r600_begin_new_cs(rctx);
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
TGSI_SEMANTIC_GENERIC,
TGSI_INTERPOLATE_CONSTANT);
rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
return &rctx->b.b;
fail:
r600_destroy_context(&rctx->b.b);
return NULL;
}
static struct pipe_context *si_create_context(struct pipe_screen *screen,
void *priv, unsigned flags)
{
struct si_context *sctx = CALLOC_STRUCT(si_context);
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->b.ws;
LLVMTargetRef r600_target;
const char *triple = "amdgcn--";
int shader, i;
if (!sctx)
return NULL;
if (sscreen->b.debug_flags & DBG_CHECK_VM)
flags |= PIPE_CONTEXT_DEBUG;
sctx->b.b.screen = screen; /* this must be set first */
sctx->b.b.priv = priv;
sctx->b.b.destroy = si_destroy_context;
sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
if (!r600_common_context_init(&sctx->b, &sscreen->b))
goto fail;
if (sscreen->b.info.drm_major == 3)
sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
si_init_blit_functions(sctx);
si_init_compute_functions(sctx);
si_init_cp_dma_functions(sctx);
si_init_debug_functions(sctx);
if (sscreen->b.info.has_uvd) {
sctx->b.b.create_video_codec = si_uvd_create_decoder;
sctx->b.b.create_video_buffer = si_video_buffer_create;
} else {
sctx->b.b.create_video_codec = vl_create_decoder;
sctx->b.b.create_video_buffer = vl_video_buffer_create;
}
sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
si_context_gfx_flush, sctx);
if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
if (!sctx->ce_ib)
goto fail;
if (ws->cs_add_const_preamble_ib) {
sctx->ce_preamble_ib =
ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
if (!sctx->ce_preamble_ib)
goto fail;
}
sctx->ce_suballocator =
u_suballocator_create(&sctx->b.b, 1024 * 1024,
64, PIPE_BIND_CUSTOM,
PIPE_USAGE_DEFAULT, FALSE);
if (!sctx->ce_suballocator)
goto fail;
}
sctx->b.gfx.flush = si_context_gfx_flush;
/* Border colors. */
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table));
if (!sctx->border_color_table)
goto fail;
sctx->border_color_buffer = (struct r600_resource*)
pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table));
if (!sctx->border_color_buffer)
goto fail;
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf,
NULL, PIPE_TRANSFER_WRITE);
if (!sctx->border_color_map)
goto fail;
si_init_all_descriptors(sctx);
si_init_state_functions(sctx);
si_init_shader_functions(sctx);
if (sctx->b.chip_class >= CIK)
cik_init_sdma_functions(sctx);
else
si_init_dma_functions(sctx);
if (sscreen->b.debug_flags & DBG_FORCE_DMA)
sctx->b.b.resource_copy_region = sctx->b.dma_copy;
sctx->blitter = util_blitter_create(&sctx->b.b);
if (sctx->blitter == NULL)
goto fail;
sctx->blitter->draw_rectangle = r600_draw_rectangle;
sctx->sample_mask.sample_mask = 0xffff;
/* these must be last */
si_begin_new_cs(sctx);
r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
* with a NULL buffer). We need to use a dummy buffer instead. */
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
PIPE_USAGE_DEFAULT, 16);
if (!sctx->null_const_buf.buffer)
goto fail;
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
&sctx->null_const_buf);
}
}
/* Clear the NULL constant buffer, because loads should return zeros. */
sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0, 0,
R600_COHERENCY_SHADER);
}
/* XXX: This is the maximum value allowed. I'm not sure how to compute
* this for non-cs shaders. Using the wrong value here can result in
* GPU lockups, but the maximum value seems to always work.
*/
sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units;
/* Initialize LLVM TargetMachine */
r600_target = radeon_llvm_get_r600_target(triple);
sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
r600_get_llvm_processor_name(sscreen->b.family),
#if HAVE_LLVM >= 0x0308
sscreen->b.debug_flags & DBG_SI_SCHED ?
"+DumpCode,+vgpr-spilling,+si-scheduler" :
#endif
"+DumpCode,+vgpr-spilling",
LLVMCodeGenLevelDefault,
LLVMRelocDefault,
LLVMCodeModelDefault);
return &sctx->b.b;
fail:
fprintf(stderr, "radeonsi: Failed to create a context.\n");
si_destroy_context(&sctx->b.b);
return NULL;
}
static struct pipe_context *si_create_context(struct pipe_screen *screen,
void *priv, unsigned flags)
{
struct si_context *sctx = CALLOC_STRUCT(si_context);
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->b.ws;
int shader, i;
if (!sctx)
return NULL;
if (sscreen->b.debug_flags & DBG_CHECK_VM)
flags |= PIPE_CONTEXT_DEBUG;
if (flags & PIPE_CONTEXT_DEBUG)
sscreen->record_llvm_ir = true; /* racy but not critical */
sctx->b.b.screen = screen; /* this must be set first */
sctx->b.b.priv = priv;
sctx->b.b.destroy = si_destroy_context;
sctx->b.b.emit_string_marker = si_emit_string_marker;
sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
if (!r600_common_context_init(&sctx->b, &sscreen->b))
goto fail;
if (sscreen->b.info.drm_major == 3)
sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
si_init_blit_functions(sctx);
si_init_compute_functions(sctx);
si_init_cp_dma_functions(sctx);
si_init_debug_functions(sctx);
if (sscreen->b.info.has_uvd) {
sctx->b.b.create_video_codec = si_uvd_create_decoder;
sctx->b.b.create_video_buffer = si_video_buffer_create;
} else {
sctx->b.b.create_video_codec = vl_create_decoder;
sctx->b.b.create_video_buffer = vl_video_buffer_create;
}
sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
si_context_gfx_flush, sctx);
if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
if (!sctx->ce_ib)
goto fail;
if (ws->cs_add_const_preamble_ib) {
sctx->ce_preamble_ib =
ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
if (!sctx->ce_preamble_ib)
goto fail;
}
sctx->ce_suballocator =
u_suballocator_create(&sctx->b.b, 1024 * 1024,
PIPE_BIND_CUSTOM,
PIPE_USAGE_DEFAULT, false);
if (!sctx->ce_suballocator)
goto fail;
}
sctx->b.gfx.flush = si_context_gfx_flush;
/* Border colors. */
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table));
if (!sctx->border_color_table)
goto fail;
sctx->border_color_buffer = (struct r600_resource*)
pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table));
if (!sctx->border_color_buffer)
goto fail;
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf,
NULL, PIPE_TRANSFER_WRITE);
if (!sctx->border_color_map)
goto fail;
si_init_all_descriptors(sctx);
si_init_state_functions(sctx);
si_init_shader_functions(sctx);
if (sctx->b.chip_class >= CIK)
cik_init_sdma_functions(sctx);
else
si_init_dma_functions(sctx);
if (sscreen->b.debug_flags & DBG_FORCE_DMA)
sctx->b.b.resource_copy_region = sctx->b.dma_copy;
sctx->blitter = util_blitter_create(&sctx->b.b);
if (sctx->blitter == NULL)
goto fail;
sctx->blitter->draw_rectangle = r600_draw_rectangle;
sctx->sample_mask.sample_mask = 0xffff;
/* these must be last */
si_begin_new_cs(sctx);
r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
* with a NULL buffer). We need to use a dummy buffer instead. */
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
PIPE_USAGE_DEFAULT, 16);
if (!sctx->null_const_buf.buffer)
goto fail;
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
&sctx->null_const_buf);
}
}
/* Clear the NULL constant buffer, because loads should return zeros. */
sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0, 0,
R600_COHERENCY_SHADER);
}
uint64_t max_threads_per_block;
screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
&max_threads_per_block);
/* The maximum number of scratch waves. Scratch space isn't divided
* evenly between CUs. The number is only a function of the number of CUs.
* We can decrease the constant to decrease the scratch buffer size.
*
* sctx->scratch_waves must be >= the maximum posible size of
* 1 threadgroup, so that the hw doesn't hang from being unable
* to start any.
*
* The recommended value is 4 per CU at most. Higher numbers don't
* bring much benefit, but they still occupy chip resources (think
* async compute). I've seen ~2% performance difference between 4 and 32.
*/
sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
max_threads_per_block / 64);
sctx->tm = si_create_llvm_target_machine(sscreen);
return &sctx->b.b;
fail:
fprintf(stderr, "radeonsi: Failed to create a context.\n");
si_destroy_context(&sctx->b.b);
return NULL;
}
struct pipe_context* r300_create_context(struct pipe_screen* screen,
void *priv)
{
struct r300_context* r300 = CALLOC_STRUCT(r300_context);
struct r300_screen* r300screen = r300_screen(screen);
struct radeon_winsys *rws = r300screen->rws;
if (!r300)
return NULL;
r300->rws = rws;
r300->screen = r300screen;
r300->context.screen = screen;
r300->context.priv = priv;
r300->context.destroy = r300_destroy_context;
util_slab_create(&r300->pool_transfers,
sizeof(struct pipe_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
r300->cs = rws->cs_create(rws, RING_GFX, r300_flush_callback, r300, NULL);
if (r300->cs == NULL)
goto fail;
if (!r300screen->caps.has_tcl) {
/* Create a Draw. This is used for SW TCL. */
r300->draw = draw_create(&r300->context);
if (r300->draw == NULL)
goto fail;
/* Enable our renderer. */
draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
/* Disable converting points/lines to triangles. */
draw_wide_line_threshold(r300->draw, 10000000.f);
draw_wide_point_threshold(r300->draw, 10000000.f);
draw_wide_point_sprites(r300->draw, FALSE);
draw_enable_line_stipple(r300->draw, TRUE);
draw_enable_point_sprites(r300->draw, FALSE);
}
if (!r300_setup_atoms(r300))
goto fail;
r300_init_blit_functions(r300);
r300_init_flush_functions(r300);
r300_init_query_functions(r300);
r300_init_state_functions(r300);
r300_init_resource_functions(r300);
r300_init_render_functions(r300);
r300_init_states(&r300->context);
r300->context.create_video_codec = vl_create_decoder;
r300->context.create_video_buffer = vl_video_buffer_create;
r300->uploader = u_upload_create(&r300->context, 256 * 1024, 4,
PIPE_BIND_CUSTOM);
r300->blitter = util_blitter_create(&r300->context);
if (r300->blitter == NULL)
goto fail;
r300->blitter->draw_rectangle = r300_blitter_draw_rectangle;
/* The KIL opcode needs the first texture unit to be enabled
* on r3xx-r4xx. In order to calm down the CS checker, we bind this
* dummy texture there. */
if (!r300->screen->caps.is_r500) {
struct pipe_resource *tex;
struct pipe_resource rtempl = {{0}};
struct pipe_sampler_view vtempl = {{0}};
rtempl.target = PIPE_TEXTURE_2D;
rtempl.format = PIPE_FORMAT_I8_UNORM;
rtempl.usage = PIPE_USAGE_IMMUTABLE;
rtempl.width0 = 1;
rtempl.height0 = 1;
rtempl.depth0 = 1;
tex = screen->resource_create(screen, &rtempl);
u_sampler_view_default_template(&vtempl, tex, tex->format);
r300->texkill_sampler = (struct r300_sampler_view*)
r300->context.create_sampler_view(&r300->context, tex, &vtempl);
pipe_resource_reference(&tex, NULL);
}
if (r300screen->caps.has_tcl) {
struct pipe_resource vb;
memset(&vb, 0, sizeof(vb));
vb.target = PIPE_BUFFER;
vb.format = PIPE_FORMAT_R8_UNORM;
vb.usage = PIPE_USAGE_DEFAULT;
vb.width0 = sizeof(float) * 16;
vb.height0 = 1;
vb.depth0 = 1;
r300->dummy_vb.buffer = screen->resource_create(screen, &vb);
r300->context.set_vertex_buffers(&r300->context, 0, 1, &r300->dummy_vb);
}
{
struct pipe_depth_stencil_alpha_state dsa;
memset(&dsa, 0, sizeof(dsa));
dsa.depth.writemask = 1;
r300->dsa_decompress_zmask =
r300->context.create_depth_stencil_alpha_state(&r300->context,
&dsa);
}
r300->hyperz_time_of_last_flush = os_time_get();
/* Register allocator state */
rc_init_regalloc_state(&r300->fs_regalloc_state);
/* Print driver info. */
#ifdef DEBUG
{
#else
if (DBG_ON(r300, DBG_INFO)) {
#endif
fprintf(stderr,
"r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
"r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n"
"r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
r300->screen->info.drm_major,
r300->screen->info.drm_minor,
r300->screen->info.drm_patchlevel,
screen->get_name(screen),
r300->screen->info.pci_id,
r300->screen->info.r300_num_gb_pipes,
r300->screen->info.r300_num_z_pipes,
r300->screen->info.gart_size >> 20,
r300->screen->info.vram_size >> 20,
"YES", /* XXX really? */
r300->screen->caps.zmask_ram ? "YES" : "NO",
r300->screen->caps.hiz_ram ? "YES" : "NO");
}
return &r300->context;
fail:
r300_destroy_context(&r300->context);
return NULL;
}
struct pipe_context *
swr_create_context(struct pipe_screen *p_screen, void *priv, unsigned flags)
{
struct swr_context *ctx = (struct swr_context *)
AlignedMalloc(sizeof(struct swr_context), KNOB_SIMD_BYTES);
memset(ctx, 0, sizeof(struct swr_context));
swr_screen(p_screen)->pfnSwrGetInterface(ctx->api);
ctx->swrDC.pAPI = &ctx->api;
ctx->blendJIT =
new std::unordered_map<BLEND_COMPILE_STATE, PFN_BLEND_JIT_FUNC>;
SWR_CREATECONTEXT_INFO createInfo;
memset(&createInfo, 0, sizeof(createInfo));
createInfo.privateStateSize = sizeof(swr_draw_context);
createInfo.pfnLoadTile = swr_LoadHotTile;
createInfo.pfnStoreTile = swr_StoreHotTile;
createInfo.pfnClearTile = swr_StoreHotTileClear;
createInfo.pfnUpdateStats = swr_UpdateStats;
createInfo.pfnUpdateStatsFE = swr_UpdateStatsFE;
ctx->swrContext = ctx->api.pfnSwrCreateContext(&createInfo);
ctx->api.pfnSwrInit();
if (ctx->swrContext == NULL)
goto fail;
ctx->pipe.screen = p_screen;
ctx->pipe.destroy = swr_destroy;
ctx->pipe.priv = priv;
ctx->pipe.create_surface = swr_create_surface;
ctx->pipe.surface_destroy = swr_surface_destroy;
ctx->pipe.transfer_map = swr_transfer_map;
ctx->pipe.transfer_unmap = swr_transfer_unmap;
ctx->pipe.transfer_flush_region = swr_transfer_flush_region;
ctx->pipe.buffer_subdata = u_default_buffer_subdata;
ctx->pipe.texture_subdata = u_default_texture_subdata;
ctx->pipe.clear_texture = util_clear_texture;
ctx->pipe.resource_copy_region = swr_resource_copy;
ctx->pipe.render_condition = swr_render_condition;
swr_state_init(&ctx->pipe);
swr_clear_init(&ctx->pipe);
swr_draw_init(&ctx->pipe);
swr_query_init(&ctx->pipe);
ctx->pipe.stream_uploader = u_upload_create_default(&ctx->pipe);
if (!ctx->pipe.stream_uploader)
goto fail;
ctx->pipe.const_uploader = ctx->pipe.stream_uploader;
ctx->pipe.blit = swr_blit;
ctx->blitter = util_blitter_create(&ctx->pipe);
if (!ctx->blitter)
goto fail;
swr_init_scratch_buffers(ctx);
return &ctx->pipe;
fail:
/* Should really validate the init steps and fail gracefully */
swr_destroy(&ctx->pipe);
return NULL;
}
static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
{
struct r600_context *rctx = CALLOC_STRUCT(r600_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
struct radeon_winsys *ws = rscreen->b.ws;
if (rctx == NULL)
return NULL;
rctx->b.b.screen = screen;
rctx->b.b.priv = priv;
rctx->b.b.destroy = r600_destroy_context;
if (!r600_common_context_init(&rctx->b, &rscreen->b))
goto fail;
rctx->screen = rscreen;
rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
r600_init_blit_functions(rctx);
if (rscreen->b.info.has_uvd) {
rctx->b.b.create_video_codec = r600_uvd_create_decoder;
rctx->b.b.create_video_buffer = r600_video_buffer_create;
} else {
rctx->b.b.create_video_codec = vl_create_decoder;
rctx->b.b.create_video_buffer = vl_video_buffer_create;
}
r600_init_common_state_functions(rctx);
switch (rctx->b.chip_class) {
case R600:
case R700:
r600_init_state_functions(rctx);
r600_init_atom_start_cs(rctx);
rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
: r600_create_resolve_blend(rctx);
rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
rctx->b.family == CHIP_RV620 ||
rctx->b.family == CHIP_RS780 ||
rctx->b.family == CHIP_RS880 ||
rctx->b.family == CHIP_RV710);
break;
case EVERGREEN:
case CAYMAN:
evergreen_init_state_functions(rctx);
evergreen_init_atom_start_cs(rctx);
evergreen_init_atom_start_compute_cs(rctx);
rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
rctx->b.family == CHIP_PALM ||
rctx->b.family == CHIP_SUMO ||
rctx->b.family == CHIP_SUMO2 ||
rctx->b.family == CHIP_CAICOS ||
rctx->b.family == CHIP_CAYMAN ||
rctx->b.family == CHIP_ARUBA);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
goto fail;
}
rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX,
r600_context_gfx_flush, rctx,
rscreen->b.trace_bo ?
rscreen->b.trace_bo->cs_buf : NULL);
rctx->b.rings.gfx.flush = r600_context_gfx_flush;
rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
0, PIPE_USAGE_DEFAULT, FALSE);
if (!rctx->allocator_fetch_shader)
goto fail;
rctx->isa = calloc(1, sizeof(struct r600_isa));
if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
goto fail;
rctx->blitter = util_blitter_create(&rctx->b.b);
if (rctx->blitter == NULL)
goto fail;
util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
rctx->blitter->draw_rectangle = r600_draw_rectangle;
r600_begin_new_cs(rctx);
r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
TGSI_SEMANTIC_GENERIC,
TGSI_INTERPOLATE_CONSTANT);
rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
return &rctx->b.b;
fail:
r600_destroy_context(&rctx->b.b);
return NULL;
}
struct pipe_context *
softpipe_create_context(struct pipe_screen *screen,
void *priv, unsigned flags)
{
struct softpipe_screen *sp_screen = softpipe_screen(screen);
struct softpipe_context *softpipe = CALLOC_STRUCT(softpipe_context);
uint i, sh;
util_init_math();
for (i = 0; i < PIPE_SHADER_TYPES; i++) {
softpipe->tgsi.sampler[i] = sp_create_tgsi_sampler();
}
for (i = 0; i < PIPE_SHADER_TYPES; i++) {
softpipe->tgsi.image[i] = sp_create_tgsi_image();
}
for (i = 0; i < PIPE_SHADER_TYPES; i++) {
softpipe->tgsi.buffer[i] = sp_create_tgsi_buffer();
}
softpipe->dump_fs = debug_get_bool_option( "SOFTPIPE_DUMP_FS", FALSE );
softpipe->dump_gs = debug_get_bool_option( "SOFTPIPE_DUMP_GS", FALSE );
softpipe->pipe.screen = screen;
softpipe->pipe.destroy = softpipe_destroy;
softpipe->pipe.priv = priv;
/* state setters */
softpipe_init_blend_funcs(&softpipe->pipe);
softpipe_init_clip_funcs(&softpipe->pipe);
softpipe_init_query_funcs( softpipe );
softpipe_init_rasterizer_funcs(&softpipe->pipe);
softpipe_init_sampler_funcs(&softpipe->pipe);
softpipe_init_shader_funcs(&softpipe->pipe);
softpipe_init_streamout_funcs(&softpipe->pipe);
softpipe_init_texture_funcs( &softpipe->pipe );
softpipe_init_vertex_funcs(&softpipe->pipe);
softpipe_init_image_funcs(&softpipe->pipe);
softpipe->pipe.set_framebuffer_state = softpipe_set_framebuffer_state;
softpipe->pipe.draw_vbo = softpipe_draw_vbo;
softpipe->pipe.clear = softpipe_clear;
softpipe->pipe.flush = softpipe_flush_wrapped;
softpipe->pipe.texture_barrier = softpipe_texture_barrier;
softpipe->pipe.memory_barrier = softpipe_memory_barrier;
softpipe->pipe.render_condition = softpipe_render_condition;
/*
* Alloc caches for accessing drawing surfaces and textures.
* Must be before quad stage setup!
*/
for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++)
softpipe->cbuf_cache[i] = sp_create_tile_cache( &softpipe->pipe );
softpipe->zsbuf_cache = sp_create_tile_cache( &softpipe->pipe );
/* Allocate texture caches */
for (sh = 0; sh < Elements(softpipe->tex_cache); sh++) {
for (i = 0; i < Elements(softpipe->tex_cache[0]); i++) {
softpipe->tex_cache[sh][i] = sp_create_tex_tile_cache(&softpipe->pipe);
if (!softpipe->tex_cache[sh][i])
goto fail;
}
}
softpipe->fs_machine = tgsi_exec_machine_create();
/* setup quad rendering stages */
softpipe->quad.shade = sp_quad_shade_stage(softpipe);
softpipe->quad.depth_test = sp_quad_depth_test_stage(softpipe);
softpipe->quad.blend = sp_quad_blend_stage(softpipe);
softpipe->quad.pstipple = sp_quad_polygon_stipple_stage(softpipe);
/*
* Create drawing context and plug our rendering stage into it.
*/
if (sp_screen->use_llvm)
softpipe->draw = draw_create(&softpipe->pipe);
else
softpipe->draw = draw_create_no_llvm(&softpipe->pipe);
if (!softpipe->draw)
goto fail;
draw_texture_sampler(softpipe->draw,
PIPE_SHADER_VERTEX,
(struct tgsi_sampler *)
softpipe->tgsi.sampler[PIPE_SHADER_VERTEX]);
draw_texture_sampler(softpipe->draw,
PIPE_SHADER_GEOMETRY,
(struct tgsi_sampler *)
softpipe->tgsi.sampler[PIPE_SHADER_GEOMETRY]);
draw_image(softpipe->draw,
PIPE_SHADER_VERTEX,
(struct tgsi_image *)
softpipe->tgsi.image[PIPE_SHADER_VERTEX]);
draw_image(softpipe->draw,
PIPE_SHADER_GEOMETRY,
(struct tgsi_image *)
softpipe->tgsi.image[PIPE_SHADER_GEOMETRY]);
draw_buffer(softpipe->draw,
PIPE_SHADER_VERTEX,
(struct tgsi_buffer *)
softpipe->tgsi.buffer[PIPE_SHADER_VERTEX]);
draw_buffer(softpipe->draw,
PIPE_SHADER_GEOMETRY,
(struct tgsi_buffer *)
softpipe->tgsi.buffer[PIPE_SHADER_GEOMETRY]);
if (debug_get_bool_option( "SOFTPIPE_NO_RAST", FALSE ))
softpipe->no_rast = TRUE;
softpipe->vbuf_backend = sp_create_vbuf_backend(softpipe);
if (!softpipe->vbuf_backend)
goto fail;
softpipe->vbuf = draw_vbuf_stage(softpipe->draw, softpipe->vbuf_backend);
if (!softpipe->vbuf)
goto fail;
draw_set_rasterize_stage(softpipe->draw, softpipe->vbuf);
draw_set_render(softpipe->draw, softpipe->vbuf_backend);
softpipe->blitter = util_blitter_create(&softpipe->pipe);
if (!softpipe->blitter) {
goto fail;
}
/* must be done before installing Draw stages */
util_blitter_cache_all_shaders(softpipe->blitter);
/* plug in AA line/point stages */
draw_install_aaline_stage(softpipe->draw, &softpipe->pipe);
draw_install_aapoint_stage(softpipe->draw, &softpipe->pipe);
/* Do polygon stipple w/ texture map + frag prog? */
#if DO_PSTIPPLE_IN_DRAW_MODULE
draw_install_pstipple_stage(softpipe->draw, &softpipe->pipe);
#endif
draw_wide_point_sprites(softpipe->draw, TRUE);
sp_init_surface_functions(softpipe);
#if DO_PSTIPPLE_IN_HELPER_MODULE
/* create the polgon stipple sampler */
softpipe->pstipple.sampler = util_pstipple_create_sampler(&softpipe->pipe);
#endif
return &softpipe->pipe;
fail:
softpipe_destroy(&softpipe->pipe);
return NULL;
}
static struct pipe_context *si_create_context(struct pipe_screen *screen,
unsigned flags)
{
struct si_context *sctx = CALLOC_STRUCT(si_context);
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->ws;
int shader, i;
bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
if (!sctx)
return NULL;
sctx->has_graphics = sscreen->info.chip_class == SI ||
!(flags & PIPE_CONTEXT_COMPUTE_ONLY);
if (flags & PIPE_CONTEXT_DEBUG)
sscreen->record_llvm_ir = true; /* racy but not critical */
sctx->b.screen = screen; /* this must be set first */
sctx->b.priv = NULL;
sctx->b.destroy = si_destroy_context;
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
sctx->ws = sscreen->ws;
sctx->family = sscreen->info.family;
sctx->chip_class = sscreen->info.chip_class;
if (sscreen->info.has_gpu_reset_counter_query) {
sctx->gpu_reset_counter =
sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
}
if (sctx->chip_class == CIK ||
sctx->chip_class == VI ||
sctx->chip_class == GFX9) {
sctx->eop_bug_scratch = si_resource(
pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
16 * sscreen->info.num_render_backends));
if (!sctx->eop_bug_scratch)
goto fail;
}
/* Initialize context allocators. */
sctx->allocator_zeroed_memory =
u_suballocator_create(&sctx->b, 128 * 1024,
0, PIPE_USAGE_DEFAULT,
SI_RESOURCE_FLAG_UNMAPPABLE |
SI_RESOURCE_FLAG_CLEAR, false);
if (!sctx->allocator_zeroed_memory)
goto fail;
sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
0, PIPE_USAGE_STREAM,
SI_RESOURCE_FLAG_READ_ONLY);
if (!sctx->b.stream_uploader)
goto fail;
sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
0, PIPE_USAGE_STAGING, 0);
if (!sctx->cached_gtt_allocator)
goto fail;
sctx->ctx = sctx->ws->ctx_create(sctx->ws);
if (!sctx->ctx)
goto fail;
if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
(void*)si_flush_dma_cs,
sctx, stop_exec_on_failure);
}
bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
0, PIPE_USAGE_DEFAULT,
SI_RESOURCE_FLAG_32BIT |
(use_sdma_upload ?
SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA :
(sscreen->cpdma_prefetch_writes_memory ?
0 : SI_RESOURCE_FLAG_READ_ONLY)));
if (!sctx->b.const_uploader)
goto fail;
if (use_sdma_upload)
u_upload_enable_flush_explicit(sctx->b.const_uploader);
sctx->gfx_cs = ws->cs_create(sctx->ctx,
sctx->has_graphics ? RING_GFX : RING_COMPUTE,
(void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
/* Border colors. */
sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table));
if (!sctx->border_color_table)
goto fail;
sctx->border_color_buffer = si_resource(
pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
SI_MAX_BORDER_COLORS *
sizeof(*sctx->border_color_table)));
if (!sctx->border_color_buffer)
goto fail;
sctx->border_color_map =
ws->buffer_map(sctx->border_color_buffer->buf,
NULL, PIPE_TRANSFER_WRITE);
if (!sctx->border_color_map)
goto fail;
/* Initialize context functions used by graphics and compute. */
sctx->b.emit_string_marker = si_emit_string_marker;
sctx->b.set_debug_callback = si_set_debug_callback;
sctx->b.set_log_context = si_set_log_context;
sctx->b.set_context_param = si_set_context_param;
sctx->b.get_device_reset_status = si_get_reset_status;
sctx->b.set_device_reset_callback = si_set_device_reset_callback;
si_init_all_descriptors(sctx);
si_init_buffer_functions(sctx);
si_init_clear_functions(sctx);
si_init_blit_functions(sctx);
si_init_compute_functions(sctx);
si_init_compute_blit_functions(sctx);
si_init_debug_functions(sctx);
si_init_fence_functions(sctx);
si_init_state_compute_functions(sctx);
if (sscreen->debug_flags & DBG(FORCE_DMA))
sctx->b.resource_copy_region = sctx->dma_copy;
/* Initialize graphics-only context functions. */
if (sctx->has_graphics) {
si_init_context_texture_functions(sctx);
si_init_query_functions(sctx);
si_init_msaa_functions(sctx);
si_init_shader_functions(sctx);
si_init_state_functions(sctx);
si_init_streamout_functions(sctx);
si_init_viewport_functions(sctx);
sctx->blitter = util_blitter_create(&sctx->b);
if (sctx->blitter == NULL)
goto fail;
sctx->blitter->skip_viewport_restore = true;
si_init_draw_functions(sctx);
}
/* Initialize SDMA functions. */
if (sctx->chip_class >= CIK)
cik_init_sdma_functions(sctx);
else
si_init_dma_functions(sctx);
sctx->sample_mask = 0xffff;
/* Initialize multimedia functions. */
if (sscreen->info.has_hw_decode) {
sctx->b.create_video_codec = si_uvd_create_decoder;
sctx->b.create_video_buffer = si_video_buffer_create;
} else {
sctx->b.create_video_codec = vl_create_decoder;
sctx->b.create_video_buffer = vl_video_buffer_create;
}
if (sctx->chip_class >= GFX9) {
sctx->wait_mem_scratch = si_resource(
pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
if (!sctx->wait_mem_scratch)
goto fail;
/* Initialize the memory. */
si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
V_370_MEM, V_370_ME, &sctx->wait_mem_number);
}
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
* if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
if (sctx->chip_class == CIK) {
sctx->null_const_buf.buffer =
pipe_aligned_buffer_create(screen,
SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT, 16,
sctx->screen->info.tcc_cache_line_size);
if (!sctx->null_const_buf.buffer)
goto fail;
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.set_constant_buffer(&sctx->b, shader, i,
&sctx->null_const_buf);
}
}
si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
&sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
&sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
&sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
&sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
&sctx->null_const_buf);
}
uint64_t max_threads_per_block;
screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
&max_threads_per_block);
/* The maximum number of scratch waves. Scratch space isn't divided
* evenly between CUs. The number is only a function of the number of CUs.
* We can decrease the constant to decrease the scratch buffer size.
*
* sctx->scratch_waves must be >= the maximum posible size of
* 1 threadgroup, so that the hw doesn't hang from being unable
* to start any.
*
* The recommended value is 4 per CU at most. Higher numbers don't
* bring much benefit, but they still occupy chip resources (think
* async compute). I've seen ~2% performance difference between 4 and 32.
*/
sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
max_threads_per_block / 64);
si_init_compiler(sscreen, &sctx->compiler);
/* Bindless handles. */
sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
_mesa_key_pointer_equal);
sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
_mesa_key_pointer_equal);
util_dynarray_init(&sctx->resident_tex_handles, NULL);
util_dynarray_init(&sctx->resident_img_handles, NULL);
util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
sctx->sample_pos_buffer =
pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
sizeof(sctx->sample_positions));
pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
sizeof(sctx->sample_positions), &sctx->sample_positions);
/* this must be last */
si_begin_new_gfx_cs(sctx);
if (sctx->chip_class == CIK) {
/* Clear the NULL constant buffer, because loads should return zeros.
* Note that this forces CP DMA to be used, because clover deadlocks
* for some reason when the compute codepath is used.
*/
uint32_t clear_value = 0;
si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0,
&clear_value, 4, SI_COHERENCY_SHADER, true);
}
return &sctx->b;
fail:
fprintf(stderr, "radeonsi: Failed to create a context.\n");
si_destroy_context(&sctx->b);
return NULL;
}
static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
{
struct si_context *sctx = CALLOC_STRUCT(si_context);
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->b.ws;
int shader, i;
if (sctx == NULL)
return NULL;
sctx->b.b.screen = screen; /* this must be set first */
sctx->b.b.priv = priv;
sctx->b.b.destroy = si_destroy_context;
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
if (!r600_common_context_init(&sctx->b, &sscreen->b))
goto fail;
si_init_blit_functions(sctx);
si_init_compute_functions(sctx);
if (sscreen->b.info.has_uvd) {
sctx->b.b.create_video_codec = si_uvd_create_decoder;
sctx->b.b.create_video_buffer = si_video_buffer_create;
} else {
sctx->b.b.create_video_codec = vl_create_decoder;
sctx->b.b.create_video_buffer = vl_video_buffer_create;
}
sctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX, si_context_gfx_flush,
sctx, NULL);
sctx->b.rings.gfx.flush = si_context_gfx_flush;
si_init_all_descriptors(sctx);
/* Initialize cache_flush. */
sctx->cache_flush = si_atom_cache_flush;
sctx->atoms.s.cache_flush = &sctx->cache_flush;
sctx->msaa_config = si_atom_msaa_config;
sctx->atoms.s.msaa_config = &sctx->msaa_config;
sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
switch (sctx->b.chip_class) {
case SI:
case CIK:
si_init_state_functions(sctx);
si_init_config(sctx);
break;
default:
R600_ERR("Unsupported chip class %d.\n", sctx->b.chip_class);
goto fail;
}
sctx->blitter = util_blitter_create(&sctx->b.b);
if (sctx->blitter == NULL)
goto fail;
sctx->blitter->draw_rectangle = r600_draw_rectangle;
sctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
TGSI_SEMANTIC_GENERIC,
TGSI_INTERPOLATE_CONSTANT);
sctx->b.b.bind_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
/* these must be last */
si_begin_new_cs(sctx);
r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
* with a NULL buffer). We need to use a dummy buffer instead. */
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
PIPE_USAGE_DEFAULT, 16);
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
&sctx->null_const_buf);
}
}
/* Clear the NULL constant buffer, because loads should return zeros. */
sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0, 0);
}
return &sctx->b.b;
fail:
si_destroy_context(&sctx->b.b);
return NULL;
}
static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
{
struct r600_context *rctx = CALLOC_STRUCT(r600_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
int shader, i;
if (rctx == NULL)
return NULL;
if (!r600_common_context_init(&rctx->b, &rscreen->b))
goto fail;
rctx->b.b.screen = screen;
rctx->b.b.priv = priv;
rctx->b.b.destroy = r600_destroy_context;
rctx->b.b.flush = r600_flush_from_st;
/* Easy accessing of screen/winsys. */
rctx->screen = rscreen;
si_init_blit_functions(rctx);
r600_init_query_functions(rctx);
r600_init_context_resource_functions(rctx);
si_init_compute_functions(rctx);
if (rscreen->b.info.has_uvd) {
rctx->b.b.create_video_codec = radeonsi_uvd_create_decoder;
rctx->b.b.create_video_buffer = radeonsi_video_buffer_create;
} else {
rctx->b.b.create_video_codec = vl_create_decoder;
rctx->b.b.create_video_buffer = vl_video_buffer_create;
}
rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
rctx->b.rings.gfx.flush = r600_flush_from_winsys;
si_init_all_descriptors(rctx);
/* Initialize cache_flush. */
rctx->cache_flush = si_atom_cache_flush;
rctx->atoms.cache_flush = &rctx->cache_flush;
rctx->atoms.streamout_begin = &rctx->b.streamout.begin_atom;
switch (rctx->b.chip_class) {
case SI:
case CIK:
si_init_state_functions(rctx);
LIST_INITHEAD(&rctx->active_nontimer_query_list);
rctx->max_db = 8;
si_init_config(rctx);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
goto fail;
}
rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
util_slab_create(&rctx->pool_transfers,
sizeof(struct pipe_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
rctx->uploader = u_upload_create(&rctx->b.b, 1024 * 1024, 256,
PIPE_BIND_INDEX_BUFFER |
PIPE_BIND_CONSTANT_BUFFER);
if (!rctx->uploader)
goto fail;
rctx->blitter = util_blitter_create(&rctx->b.b);
if (rctx->blitter == NULL)
goto fail;
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
TGSI_SEMANTIC_GENERIC,
TGSI_INTERPOLATE_CONSTANT);
rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
/* these must be last */
si_begin_new_cs(rctx);
si_get_backend_mask(rctx);
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
* with a NULL buffer). We need to use a dummy buffer instead. */
if (rctx->b.chip_class == CIK) {
rctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
PIPE_USAGE_STATIC, 16);
rctx->null_const_buf.buffer_size = rctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < NUM_CONST_BUFFERS; i++) {
rctx->b.b.set_constant_buffer(&rctx->b.b, shader, i,
&rctx->null_const_buf);
}
}
/* Clear the NULL constant buffer, because loads should return zeros. */
rctx->b.clear_buffer(&rctx->b.b, rctx->null_const_buf.buffer, 0,
rctx->null_const_buf.buffer->width0, 0);
}
return &rctx->b.b;
fail:
r600_destroy_context(&rctx->b.b);
return NULL;
}
static struct pipe_context *si_create_context(struct pipe_screen *screen, void *priv)
{
struct si_context *sctx = CALLOC_STRUCT(si_context);
struct si_screen* sscreen = (struct si_screen *)screen;
struct radeon_winsys *ws = sscreen->b.ws;
LLVMTargetRef r600_target;
#if HAVE_LLVM >= 0x0306
const char *triple = "amdgcn--";
#endif
int shader, i;
if (sctx == NULL)
return NULL;
sctx->b.b.screen = screen; /* this must be set first */
sctx->b.b.priv = priv;
sctx->b.b.destroy = si_destroy_context;
sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
if (!r600_common_context_init(&sctx->b, &sscreen->b))
goto fail;
if (sscreen->b.info.drm_major == 3)
sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
si_init_blit_functions(sctx);
si_init_compute_functions(sctx);
si_init_cp_dma_functions(sctx);
if (sscreen->b.info.has_uvd) {
sctx->b.b.create_video_codec = si_uvd_create_decoder;
sctx->b.b.create_video_buffer = si_video_buffer_create;
} else {
sctx->b.b.create_video_codec = vl_create_decoder;
sctx->b.b.create_video_buffer = vl_video_buffer_create;
}
sctx->b.rings.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX, si_context_gfx_flush,
sctx, sscreen->b.trace_bo ?
sscreen->b.trace_bo->cs_buf : NULL);
sctx->b.rings.gfx.flush = si_context_gfx_flush;
si_init_all_descriptors(sctx);
/* Initialize cache_flush. */
sctx->cache_flush = si_atom_cache_flush;
sctx->atoms.s.cache_flush = &sctx->cache_flush;
sctx->msaa_sample_locs = si_atom_msaa_sample_locs;
sctx->atoms.s.msaa_sample_locs = &sctx->msaa_sample_locs;
sctx->msaa_config = si_atom_msaa_config;
sctx->atoms.s.msaa_config = &sctx->msaa_config;
sctx->atoms.s.streamout_begin = &sctx->b.streamout.begin_atom;
sctx->atoms.s.streamout_enable = &sctx->b.streamout.enable_atom;
si_init_state_functions(sctx);
si_init_shader_functions(sctx);
if (sscreen->b.debug_flags & DBG_FORCE_DMA)
sctx->b.b.resource_copy_region = sctx->b.dma_copy;
sctx->blitter = util_blitter_create(&sctx->b.b);
if (sctx->blitter == NULL)
goto fail;
sctx->blitter->draw_rectangle = r600_draw_rectangle;
/* these must be last */
si_begin_new_cs(sctx);
r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
* with a NULL buffer). We need to use a dummy buffer instead. */
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
PIPE_USAGE_DEFAULT, 16);
if (!sctx->null_const_buf.buffer)
goto fail;
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
&sctx->null_const_buf);
}
}
/* Clear the NULL constant buffer, because loads should return zeros. */
sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
sctx->null_const_buf.buffer->width0, 0, false);
}
/* XXX: This is the maximum value allowed. I'm not sure how to compute
* this for non-cs shaders. Using the wrong value here can result in
* GPU lockups, but the maximum value seems to always work.
*/
sctx->scratch_waves = 32 * sscreen->b.info.max_compute_units;
#if HAVE_LLVM >= 0x0306
/* Initialize LLVM TargetMachine */
r600_target = radeon_llvm_get_r600_target(triple);
sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
r600_get_llvm_processor_name(sscreen->b.family),
"+DumpCode,+vgpr-spilling",
LLVMCodeGenLevelDefault,
LLVMRelocDefault,
LLVMCodeModelDefault);
#endif
return &sctx->b.b;
fail:
si_destroy_context(&sctx->b.b);
return NULL;
}
struct pipe_context *
swr_create_context(struct pipe_screen *p_screen, void *priv, unsigned flags)
{
struct swr_context *ctx = (struct swr_context *)
AlignedMalloc(sizeof(struct swr_context), KNOB_SIMD_BYTES);
memset(ctx, 0, sizeof(struct swr_context));
swr_screen(p_screen)->pfnSwrGetInterface(ctx->api);
ctx->swrDC.pAPI = &ctx->api;
ctx->blendJIT =
new std::unordered_map<BLEND_COMPILE_STATE, PFN_BLEND_JIT_FUNC>;
ctx->max_draws_in_flight = KNOB_MAX_DRAWS_IN_FLIGHT;
SWR_CREATECONTEXT_INFO createInfo;
memset(&createInfo, 0, sizeof(createInfo));
createInfo.privateStateSize = sizeof(swr_draw_context);
createInfo.pfnLoadTile = swr_LoadHotTile;
createInfo.pfnStoreTile = swr_StoreHotTile;
createInfo.pfnClearTile = swr_StoreHotTileClear;
createInfo.pfnUpdateStats = swr_UpdateStats;
createInfo.pfnUpdateStatsFE = swr_UpdateStatsFE;
SWR_THREADING_INFO threadingInfo {0};
threadingInfo.MAX_WORKER_THREADS = KNOB_MAX_WORKER_THREADS;
threadingInfo.MAX_NUMA_NODES = KNOB_MAX_NUMA_NODES;
threadingInfo.MAX_CORES_PER_NUMA_NODE = KNOB_MAX_CORES_PER_NUMA_NODE;
threadingInfo.MAX_THREADS_PER_CORE = KNOB_MAX_THREADS_PER_CORE;
threadingInfo.SINGLE_THREADED = KNOB_SINGLE_THREADED;
// Use non-standard settings for KNL
if (swr_screen(p_screen)->is_knl)
{
if (nullptr == getenv("KNOB_MAX_THREADS_PER_CORE"))
threadingInfo.MAX_THREADS_PER_CORE = 2;
if (nullptr == getenv("KNOB_MAX_DRAWS_IN_FLIGHT"))
{
ctx->max_draws_in_flight = 2048;
createInfo.MAX_DRAWS_IN_FLIGHT = ctx->max_draws_in_flight;
}
}
createInfo.pThreadInfo = &threadingInfo;
ctx->swrContext = ctx->api.pfnSwrCreateContext(&createInfo);
ctx->api.pfnSwrInit();
if (ctx->swrContext == NULL)
goto fail;
ctx->pipe.screen = p_screen;
ctx->pipe.destroy = swr_destroy;
ctx->pipe.priv = priv;
ctx->pipe.create_surface = swr_create_surface;
ctx->pipe.surface_destroy = swr_surface_destroy;
ctx->pipe.transfer_map = swr_transfer_map;
ctx->pipe.transfer_unmap = swr_transfer_unmap;
ctx->pipe.transfer_flush_region = swr_transfer_flush_region;
ctx->pipe.buffer_subdata = u_default_buffer_subdata;
ctx->pipe.texture_subdata = u_default_texture_subdata;
ctx->pipe.clear_texture = util_clear_texture;
ctx->pipe.resource_copy_region = swr_resource_copy;
ctx->pipe.render_condition = swr_render_condition;
swr_state_init(&ctx->pipe);
swr_clear_init(&ctx->pipe);
swr_draw_init(&ctx->pipe);
swr_query_init(&ctx->pipe);
ctx->pipe.stream_uploader = u_upload_create_default(&ctx->pipe);
if (!ctx->pipe.stream_uploader)
goto fail;
ctx->pipe.const_uploader = ctx->pipe.stream_uploader;
ctx->pipe.blit = swr_blit;
ctx->blitter = util_blitter_create(&ctx->pipe);
if (!ctx->blitter)
goto fail;
swr_init_scratch_buffers(ctx);
return &ctx->pipe;
fail:
/* Should really validate the init steps and fail gracefully */
swr_destroy(&ctx->pipe);
return NULL;
}
