static int fc6100_tvp5150_s_power(struct v4l2_subdev *subdev, u32 on)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
if (on) {
/* Enable EXTCLK */
if (isp->platform_cb.set_xclk)
isp->platform_cb.set_xclk(isp, 27000000, 1);
mdelay(50);
#ifdef CONFIG_PM
/*
* Through-put requirement:
* Set max OCP freq for 3630 is 200 MHz through-put
* is in KByte/s so 200000 KHz * 4 = 800000 KByte/s
*/
omap_pm_set_min_bus_tput(isp->dev, OCP_INITIATOR_AGENT,
800000);
#endif
} else {
if (isp->platform_cb.set_xclk)
isp->platform_cb.set_xclk(isp, 0, 1);
#ifdef CONFIG_PM
/* Remove pm constraints */
omap_pm_set_min_bus_tput(isp->dev, OCP_INITIATOR_AGENT, 0);
#endif
}
return 0;
}
static int m2_soc1040_set_xclk(struct v4l2_subdev *subdev, int hz)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
isp->platform_cb.set_xclk(isp, hz, SOC1040_XCLK);
return hz;
}
static u32 m2_ov7670_set_xclk(struct v4l2_subdev *subdev, u32 hz)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
isp->platform_cb.set_xclk(isp, hz, OV7670_XCLK);
return hz;
}
static int beagle_mt9v113_configure_interface(struct v4l2_subdev *subdev,
u32 pixclk)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
if (isp->platform_cb.set_pixel_clock)
isp->platform_cb.set_pixel_clock(isp, pixclk);
return 0;
}
static int beagle_mt9v113_s_power(struct v4l2_subdev *subdev, int on)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
if (!beagle_1v8 || !beagle_2v8) {
dev_err(isp->dev, "No regulator available\n");
return -ENODEV;
}
if (on) {
/*
* Power Up Sequence
*/
/* Set RESET_BAR to 0 */
gpio_set_value(LEOPARD_RESET_GPIO, 0);
/* Turn on VDD */
regulator_enable(beagle_1v8);
mdelay(1);
regulator_enable(beagle_2v8);
mdelay(50);
/* Enable EXTCLK */
if (isp->platform_cb.set_xclk)
isp->platform_cb.set_xclk(isp, 24000000, CAM_USE_XCLKA);
/*
* Wait at least 70 CLK cycles (w/EXTCLK = 24MHz):
* ((1000000 * 70) / 24000000) = aprox 3 us.
*/
udelay(3);
/* Set RESET_BAR to 1 */
gpio_set_value(LEOPARD_RESET_GPIO, 1);
/*
* Wait at least 100 CLK cycles (w/EXTCLK = 24MHz):
* ((1000000 * 100) / 24000000) = aprox 5 us.
*/
udelay(5);
} else {
/*
* Power Down Sequence
*/
if (regulator_is_enabled(beagle_1v8))
regulator_disable(beagle_1v8);
if (regulator_is_enabled(beagle_2v8))
regulator_disable(beagle_2v8);
if (isp->platform_cb.set_xclk)
isp->platform_cb.set_xclk(isp, 0, CAM_USE_XCLKA);
}
return 0;
}
static void m2_soc1040_csi2_configure(struct v4l2_subdev *subdev,
int mode)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
struct isp_csiphy_dphy_cfg csi2phy;
csi2phy.ths_term = SOC1040_CSI2_PHY_THS_TERM;
csi2phy.ths_settle = SOC1040_CSI2_PHY_THS_SETTLE;
csi2phy.tclk_term = SOC1040_CSI2_PHY_TCLK_TERM;
csi2phy.tclk_miss = SOC1040_CSI2_PHY_TCLK_MISS;
csi2phy.tclk_settle = SOC1040_CSI2_PHY_TCLK_SETTLE;
isp->platform_cb.csiphy_config(&isp->isp_csiphy2, &csi2phy,
&m2_soc1040_csi2_lanecfg);
}
static void mt9v032_set_clock(struct v4l2_subdev *subdev, unsigned int rate)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
isp->platform_cb.set_xclk(isp, rate, ISP_XCLK_A);
}
static int beagle_cam_set_xclk(struct v4l2_subdev *subdev, int hz)
{
struct isp_device *isp = v4l2_dev_to_isp_device(subdev->v4l2_dev);
return isp->platform_cb.set_xclk(isp, hz, AR0130_XCLK);
}
