static inline void cle266_set_primary_pll_encoded(u32 data) { via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ via_write_reg(VIASR, 0x46, data & 0xFF); via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF); via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ }
static inline void cle266_set_secondary_pll_encoded(u32 data) { via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ via_write_reg(VIASR, 0x44, data & 0xFF); via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ }
static inline void set_engine_pll_encoded(u32 data) { via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */ via_write_reg(VIASR, 0x47, data & 0xFF); via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF); via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF); via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */ }
static inline void k800_set_secondary_pll_encoded(u32 data) { via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ via_write_reg(VIASR, 0x4A, data & 0xFF); via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF); via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF); via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ }
static inline void k800_set_primary_pll_encoded(u32 data) { via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); via_write_reg(VIASR, 0x44, data & 0xFF); via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF); via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); }