C++ (Cpp) vlv_gpio_nc_write示例

示例#1

文件： intel_dsi.c 项目： paulalesius/kernel-3.10.20-lenovo-tablet

void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	u32 val;

	DRM_DEBUG_KMS("\n");

	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER | DEVICE_READY,
							ULPS_STATE_MASK | DEVICE_READY);
	usleep_range(2000, 2500);

	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT | DEVICE_READY,
							ULPS_STATE_MASK | DEVICE_READY);
	usleep_range(2000, 2500);

	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER | DEVICE_READY,
							ULPS_STATE_MASK | DEVICE_READY);
	usleep_range(2000, 2500);

	if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & 0x20000)
					== 0x00000), 30))
		DRM_ERROR("DSI LP not going Low\n");

	I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), 0, LP_OUTPUT_HOLD);
	usleep_range(1000, 1500);

	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00, DEVICE_READY);
	usleep_range(2000, 2500);

	intel_disable_dsi_pll(intel_dsi);

	val = I915_READ(DSPCLK_GATE_D);
	val &= ~VSUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, val);

	if (intel_dsi->dev.dev_ops->disable_panel_power)
		intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);

#ifdef CONFIG_CRYSTAL_COVE
	if (BYT_CR_CONFIG) {
		/* Disable Panel */
		vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
		vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004);
		udelay(500);
	} else
		intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x00);
#else
	/* need to code for BYT-CR for example where things have changed */
	DRM_ERROR("PANEL Disable to supported yet\n");
#endif
	msleep(intel_dsi->panel_off_delay);
	msleep(intel_dsi->panel_pwr_cycle_delay);
}

示例#2

文件： dsi_mod_auo_b080xat.c 项目： raininja/android_kernel_asus_a500cg

void b080xat_disable_panel_power(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	vlv_gpio_nc_write(dev_priv, 0x4160, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, 0x4168, 0x00000004);
	udelay(500);
}

示例#3

文件： dsi_mod_auo_b080xat.c 项目： raininja/android_kernel_asus_a500cg

void b080xat_panel_reset(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	vlv_gpio_nc_write(dev_priv, 0x4160, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, 0x4168, 0x00000004);
	udelay(500);
	vlv_gpio_nc_write(dev_priv, 0x4168, 0x00000005);
	usleep_range(10000, 12000);

}

示例#4

文件： dsi_mod_innolux_n080ice_gb1.c 项目： NotKit/android-ia_kernel_intel_baytrail

void n080ice_gb1_panel_reset(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	
	DRM_DEBUG_KMS("\n");
	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000005);
	msleep(20);
	/* panel disable */
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004);
	usleep_range(100000, 120000);
	
	/* panel enable */
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
	usleep_range(100000, 120000);
	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
	msleep(20);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000005);
	msleep(5);
}

示例#5

文件： dsi_mod_p088pw.c 项目： yutokt/android_kernel_intel_anzhen4

void p088pw_reset(struct intel_dsi_device *dsi)
{
    int val;
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	DRM_DEBUG_KMS("\n");
	//printk("p088pw_reset\n");
	val = intel_mid_pmic_readb(0x12);
    val |= 1<<5;
	intel_mid_pmic_writeb(0x12, val);
    usleep_range(100000, 120000);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);//reset
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
	usleep_range(100000, 120000);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PCONF0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PAD, 0x00000005);
	usleep_range(100000, 120000);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
	msleep(10);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000005);
}

示例#6

文件： dsi_mod_hannstar_vid.c 项目： RezaSR/android_kernel_asus_tf303cl

void hannstar_panel_reset(struct intel_dsi_device *dsi)
{
	DRM_DEBUG("[DISPLAY] %s: Enter\n", __func__);
	if (BYT_CR_CONFIG) {
		struct intel_dsi *intel_dsi = container_of(dsi,
						struct intel_dsi, dev);
		struct drm_device *dev = intel_dsi->base.base.dev;
		struct drm_i915_private *dev_priv = dev->dev_private;

		/* CABC disable */
		vlv_gpio_nc_write(dev_priv, 0x4100, 0x2000CC00);
		vlv_gpio_nc_write(dev_priv, 0x4108, 0x00000004);

		/* panel enable */
		vlv_gpio_nc_write(dev_priv, 0x40F0, 0x2000CC00);
		vlv_gpio_nc_write(dev_priv, 0x40F8, 0x00000005);
	} else

示例#7

文件： dsi_mod_kd080d14.c 项目： yutokt/android_kernel_intel_anzhen4

static void kd080d14_disable(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	DRM_DEBUG_KMS("\n");
	printk("--->%s\n",__func__);
	msleep(200);
	dsi_vc_dcs_write_0(intel_dsi, 0, 0x28);
	msleep(80);
	//dsi_vc_dcs_write(intel_dsi, 0, cpt_disable_ic_power, sizeof(cpt_disable_ic_power));
	dsi_vc_dcs_write_0(intel_dsi, 0, 0x10);
	msleep(34);
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);	
	usleep_range(100000, 120000);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004);
}

示例#8

文件： dsi_mod_p088pw.c 项目： yutokt/android_kernel_intel_anzhen4

static void p088pw_disable(struct intel_dsi_device *dsi)
{
    int val = 0;
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	DRM_DEBUG_KMS("\n");
	printk("p088pw_disable\n");
	msleep(200);
	dsi_vc_dcs_write_0(intel_dsi, 0, 0x28);
	msleep(80);

	dsi_vc_dcs_write_0(intel_dsi, 0, 0x10);
	msleep(34);
	val = intel_mid_pmic_readb(0x12);    	
	val &= ~(1<<5);		
	intel_mid_pmic_writeb(0x12, val);		
	usleep_range(100000, 120000);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);	
	usleep_range(100000, 120000);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PCONF0, 0x2000CC00);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PAD, 0x00000004);	
	usleep_range(100000, 120000);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);	
	vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004);
}

示例#9

文件： dsi_mod_boe_bp080wx7.c 项目： yutokt/android_kernel_intel_anzhen4

void bp080wx7_panel_reset(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	DRM_DEBUG_KMS("\n");

	vlv_gpio_nc_write(dev_priv, 0x4100, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, 0x4108, 0x00000004);

	/* panel disable */
	vlv_gpio_nc_write(dev_priv, 0x40F0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, 0x40F8, 0x00000004);
	usleep_range(100000, 120000);

	/* panel enable */
	vlv_gpio_nc_write(dev_priv, 0x40F0, 0x2000CC00);
	vlv_gpio_nc_write(dev_priv, 0x40F8, 0x00000005);
	usleep_range(100000, 120000);
	vlv_gpio_nc_write(dev_priv, 0x4108, 0x00000005);
}

示例#10

文件： intel_dsi.c 项目： paulalesius/kernel-3.10.20-lenovo-tablet

void intel_dsi_device_ready(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	u32 tmp;

	DRM_DEBUG_KMS("\n");

	/* program rcomp for compliance
	 * reduce form 50 ohms to 45 ohms */
	intel_flisdsi_write32(dev_priv, 0x04, 0x00f0);

	band_gap_reset(dev_priv);

#ifdef CONFIG_CRYSTAL_COVE
	/* Panel Enable */
	if (BYT_CR_CONFIG) {
		/*  cabc disable */
		vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
		vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);

		/* panel enable */
		vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
		vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
		udelay(500);
	} else
		intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);

#else
	/* need to code for BYT-CR for example where things have changed */
	DRM_ERROR("PANEL Enable to supported yet\n");
#endif
	msleep(intel_dsi->panel_on_delay);

	if (intel_dsi->dev.dev_ops->panel_reset)
		intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);

	/* Disable DPOunit clock gating, can stall pipe */
	tmp = I915_READ(DPLL(pipe));
	tmp |= DPLL_RESERVED_BIT;
	I915_WRITE(DPLL(pipe), tmp);

	tmp = I915_READ(DSPCLK_GATE_D);
	tmp |= VSUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, tmp);

	intel_enable_dsi_pll(intel_dsi);

    //in dual display config, dsi 0 is not init. so this function may not
    //be called with pipe0. set this flag for pipe0 so that pipe b can work
    #ifdef BYT_DUAL_MIPI_DSI  
    if(pipe != 0)
    {

        I915_WRITE_BITS(MIPI_PORT_CTRL(0), LP_OUTPUT_HOLD,
                LP_OUTPUT_HOLD);

        usleep_range(1000, 1500);
    }
    #endif


	I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
						LP_OUTPUT_HOLD);

	usleep_range(1000, 1500);
	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
			ULPS_STATE_EXIT, DEVICE_READY |
			ULPS_STATE_MASK);

	usleep_range(2000, 2500);
	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
			DEVICE_READY | ULPS_STATE_MASK);
	usleep_range(2000, 2500);
	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
			DEVICE_READY | ULPS_STATE_MASK);
	usleep_range(2000, 2500);
	I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
			DEVICE_READY | ULPS_STATE_MASK);
	usleep_range(2000, 2500);
}

示例#11

文件： intel_dsi.c 项目： BitOBSessiOn/android_kernel_asus_P01M

void intel_dsi_device_ready(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	u32 tmp;
	int count = 1;

	DRM_DEBUG_KMS("\n");

	/* program rcomp for compliance
	 * reduce form 50 ohms to 45 ohms */
	intel_flisdsi_write32(dev_priv, 0x04, 0x0004);

	band_gap_reset(dev_priv);

#ifdef CONFIG_CRYSTAL_COVE
	if (BYT_CR_CONFIG) {
		/*  cabc disable */
		vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
		vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);

		/* panel enable */
		vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
		vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
		udelay(500);
	} else
		intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);
#else
	/* need to code for BYT-CR for example where things have changed */
	DRM_ERROR("PANEL Enable to supported yet\n");
#endif
	msleep(intel_dsi->panel_on_delay);

	if (intel_dsi->dev.dev_ops->panel_reset)
		intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);

	/* Disable DPOunit clock gating, can stall pipe */
	tmp = I915_READ(DPLL(pipe));
	tmp |= DPLL_RESERVED_BIT;
	I915_WRITE(DPLL(pipe), tmp);

	tmp = I915_READ(DSPCLK_GATE_D);
	tmp |= VSUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, tmp);

	intel_enable_dsi_pll(intel_dsi);
	if (intel_dsi->operation_mode == DSI_VIDEO_MODE) {

		I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
							LP_OUTPUT_HOLD);

		usleep_range(1000, 1500);

		if (intel_dsi->dual_link)
			count = 2;
		do {

			I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
					ULPS_STATE_EXIT, DEVICE_READY |
					ULPS_STATE_MASK);

			usleep_range(2000, 2500);
			I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
					DEVICE_READY | ULPS_STATE_MASK);
			usleep_range(2000, 2500);
			I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
					DEVICE_READY | ULPS_STATE_MASK);
			usleep_range(2000, 2500);
			I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
					DEVICE_READY | ULPS_STATE_MASK);
			usleep_range(2000, 2500);
			/* For Port C for dual link */
			pipe = PIPE_B;
		} while (--count > 0);
	}
}