void __init vmi_time_init(void) { /* Disable PIT: BIOSes start PIT CH0 with 18.2hz peridic. */ outb_p(0x3a, PIT_MODE); /* binary, mode 5, LSB/MSB, ch 0 */ vmi_time_init_clockevent(); setup_irq(0, &vmi_clock_action); }
void __init vmi_time_init(void) { unsigned int cpu; /* Disable PIT: BIOSes start PIT CH0 with 18.2hz peridic. */ outb_pit(0x3a, PIT_MODE); /* binary, mode 5, LSB/MSB, ch 0 */ vmi_time_init_clockevent(); setup_irq(0, &vmi_clock_action); for_each_possible_cpu(cpu) per_cpu(vector_irq, cpu)[vmi_get_timer_vector()] = 0; }
void __devinit vmi_time_ap_init(void) { vmi_time_init_clockevent(); apic_write(APIC_LVTT, vmi_get_timer_vector()); }