static int hardware_enable(int slot)
{
u32 socket_status;
u16 brg_ctrl;
int is_82365sl;
socket_status = readl(socket_base+8);
if ((socket_status & 6) == 0) {
switch (socket_status & 0x3c00) {
case 0x400:
printf("5V ");
voltage_set(slot, 50, 0);
break;
case 0x800:
voltage_set(slot, 33, 0);
break;
case 0xc00:
voltage_set(slot, 33, 0);
break;
default:
voltage_set(slot, 0, 0);
break;
}
} else {
voltage_set(slot, 0, 0);
}
pci_read_config_word(devbusfn, PCI_BRIDGE_CONTROL, &brg_ctrl);
brg_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_word(devbusfn, PCI_BRIDGE_CONTROL, brg_ctrl);
is_82365sl = ((readb(socket_base+0x800) & 0x0f) == 2);
writeb(is_82365sl?0x90:0x98, socket_base+0x802);
writeb(0x67, socket_base+0x803);
udelay(100000);
#if 0
printf("ExCA Id %02x, Card Status %02x, Power config %02x, Interrupt Config %02x, bridge control %04x %d\n",
readb(socket_base+0x800), readb(socket_base+0x801),
readb(socket_base+0x802), readb(socket_base+0x803), brg_ctrl, is_82365sl);
#endif
return ((readb(socket_base+0x801)&0x6c)==0x6c)?0:1;
}
static void pcmcia_off (void)
{
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
/* turn off voltage */
voltage_set(_slot_, 0, 0);
/* disable external hardware */
printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
hardware_disable(_slot_);
}
int pcmcia_on (void)
{
PCMCIA_DEBUG ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
/* turn off voltage */
if (voltage_set(_slot_, 0, 0))
return (1);
/* Enable external hardware */
if (hardware_enable(_slot_))
return (1);
#ifdef CONFIG_IDE_PCCARD
if (check_ide_device())
return (1);
#endif
return (0);
}
static int pcmcia_off (void)
{
int slot = 0;
writeb(0x00, socket_base + 0x806); /* disable all I/O and memory windows */
writeb(0x00, socket_base + 0x808); /* I/O window 0 base address */
writeb(0x00, socket_base + 0x809);
writeb(0x00, socket_base + 0x80a); /* I/O window 0 end address */
writeb(0x00, socket_base + 0x80b);
writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address */
writeb(0x00, socket_base + 0x837);
writeb(0x00, socket_base + 0x80c); /* I/O window 1 base address */
writeb(0x00, socket_base + 0x80d);
writeb(0x00, socket_base + 0x80e); /* I/O window 1 end address */
writeb(0x00, socket_base + 0x80f);
writeb(0x00, socket_base + 0x838); /* I/O window 1 offset address */
writeb(0x00, socket_base + 0x839);
writeb(0x00, socket_base + 0x810); /* Memory window 0 start address */
writeb(0x00, socket_base + 0x811);
writeb(0x00, socket_base + 0x812); /* Memory window 0 end address */
writeb(0x00, socket_base + 0x813);
writeb(0x00, socket_base + 0x814); /* Memory window 0 offset */
writeb(0x00, socket_base + 0x815);
writeb(0xc0, socket_base + 0x840); /* Memory window 0 page address */
/* turn off voltage */
voltage_set(slot, 0, 0);
/* disable external hardware */
printf ("Shutdown and Poweroff Ti PCI1410A\n");
hardware_disable(slot);
return 0;
}
static int voltage_set(int slot, int vcc, int vpp)
{
u32 socket_control;
int reg=0;
switch (slot) {
case 0:
reg = socket_base + 0x10;
break;
default:
return 1;
}
socket_control = 0;
switch (vcc) {
case 50:
socket_control |= 0x20;
break;
case 33:
socket_control |= 0x30;
break;
case 0:
default:
}
switch (vpp) {
case 120:
socket_control |= 0x1;
break;
case 50:
socket_control |= 0x2;
break;
case 33:
socket_control |= 0x3;
break;
case 0:
default:
}
writel(socket_control, reg);
debug ("voltage_set: Ti PCI1410A Slot %d, Vcc=%d.%d, Vpp=%d.%d\n",
slot, vcc/10, vcc%10, vpp/10, vpp%10);
udelay(500);
return 0;
}
static int hardware_enable(int slot)
{
u32 socket_status;
u16 brg_ctrl;
int is_82365sl;
socket_status = readl(socket_base+8);
if ((socket_status & 6) == 0) {
switch (socket_status & 0x3c00) {
case 0x400:
printf("5V ");
voltage_set(slot, 50, 0);
break;
case 0x800:
voltage_set(slot, 33, 0);
break;
case 0xc00:
voltage_set(slot, 33, 0);
break;
default:
voltage_set(slot, 0, 0);
break;
}
} else {
voltage_set(slot, 0, 0);
}
pci_read_config_word(devbusfn, PCI_BRIDGE_CONTROL, &brg_ctrl);
brg_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_word(devbusfn, PCI_BRIDGE_CONTROL, brg_ctrl);
is_82365sl = ((readb(socket_base+0x800) & 0x0f) == 2);
writeb(is_82365sl?0x90:0x98, socket_base+0x802);
writeb(0x67, socket_base+0x803);
udelay(100000);
#if 0
printf("ExCA Id %02x, Card Status %02x, Power config %02x, Interrupt Config %02x, bridge control %04x %d\n",
readb(socket_base+0x800), readb(socket_base+0x801),
readb(socket_base+0x802), readb(socket_base+0x803), brg_ctrl, is_82365sl);
#endif
return ((readb(socket_base+0x801)&0x6c)==0x6c)?0:1;
}
static int hardware_disable(int slot)
{
voltage_set(slot, 0, 0);
return 0;
}
int pcmcia_on(int ide_base_bus)
{
u16 dev_id;
u32 socket_status;
int slot = 0;
int cis_len;
u16 io_base;
u16 io_len;
/*
* Find the CardBus PCI device(s).
*/
if ((devbusfn = pci_find_devices(supported, 0)) < 0) {
printf("Ti CardBus: not found\n");
return 1;
}
pci_read_config_word(devbusfn, PCI_DEVICE_ID, &dev_id);
if (dev_id == 0xac56) {
debug("Enable PCMCIA Ti PCI1510\n");
} else {
debug("Enable PCMCIA Ti PCI1410A\n");
}
pcmcia_cis_ptr = CFG_PCMCIA_CIS_WIN;
cis_len = CFG_PCMCIA_CIS_WIN_SIZE;
io_base = CFG_PCMCIA_IO_WIN;
io_len = CFG_PCMCIA_IO_WIN_SIZE;
/*
* Setup the PCI device.
*/
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &socket_base);
socket_base &= ~0xf;
socket_status = readl(socket_base+8);
if ((socket_status & 6) == 0) {
printf("Card Present: ");
switch (socket_status & 0x3c00) {
case 0x400:
printf("5V ");
break;
case 0x800:
printf("3.3V ");
break;
case 0xc00:
printf("3.3/5V ");
break;
default:
printf("unsupported Vcc ");
break;
}
switch (socket_status & 0x30) {
case 0x10:
printf("16bit PC-Card\n");
break;
case 0x20:
printf("32bit CardBus Card\n");
break;
default:
printf("8bit PC-Card\n");
break;
}
}
writeb(0x41, socket_base + 0x806); /* Enable I/O window 0 and memory window 0 */
writeb(0x0e, socket_base + 0x807); /* Reset I/O window options */
/* Careful: the linux yenta driver do not seem to reset the offset
* in the i/o windows, so leaving them non-zero is a problem */
writeb(io_base & 0xff, socket_base + 0x808); /* I/O window 0 base address */
writeb(io_base>>8, socket_base + 0x809);
writeb((io_base + io_len - 1) & 0xff, socket_base + 0x80a); /* I/O window 0 end address */
writeb((io_base + io_len - 1)>>8, socket_base + 0x80b);
writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address 0x000 */
writeb(0x00, socket_base + 0x837);
writeb((pcmcia_cis_ptr&0x000ff000) >> 12,
socket_base + 0x810); /* Memory window 0 start address bits 19-12 */
writeb((pcmcia_cis_ptr&0x00f00000) >> 20,
socket_base + 0x811); /* Memory window 0 start address bits 23-20 */
writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12,
socket_base + 0x812); /* Memory window 0 end address bits 19-12*/
writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20,
socket_base + 0x813); /* Memory window 0 end address bits 23-20*/
writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */
writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and
* options (read/write, attribute access) */
writeb(0x00, socket_base + 0x816); /* ExCA card-detect and general control */
writeb(0x00, socket_base + 0x81e); /* ExCA global control (interrupt modes) */
writeb((pcmcia_cis_ptr & 0xff000000) >> 24,
socket_base + 0x840); /* Memory window address bits 31-24 */
/* turn off voltage */
if (voltage_set(slot, 0, 0)) {
return 1;
}
/* Enable external hardware */
if (hardware_enable(slot)) {
return 1;
}
if (check_ide_device(slot, ide_base_bus)) {
return 1;
}
return 0;
}
static int hardware_disable(int slot)
{
voltage_set(slot, 0, 0);
return 0;
}
