static void __devinit smp_xics_setup_cpu(int cpu) { if (cpu != boot_cpuid) xics_setup_cpu(); if (firmware_has_feature(FW_FEATURE_SPLPAR)) vpa_init(cpu); cpu_clear(cpu, of_spin_map); }
static void __devinit smp_xics_setup_cpu(int cpu) { if (cpu != boot_cpuid) xics_setup_cpu(); if (firmware_has_feature(FW_FEATURE_SPLPAR)) vpa_init(cpu); cpumask_clear_cpu(cpu, of_spin_mask); set_cpu_current_state(cpu, CPU_STATE_ONLINE); set_default_offline_state(cpu); }
static void __devinit smp_xics_setup_cpu(int cpu) { if (cpu != boot_cpuid) xics_setup_cpu(); if (firmware_has_feature(FW_FEATURE_SPLPAR)) vpa_init(cpu); cpumask_clear_cpu(cpu, of_spin_mask); #ifdef CONFIG_HOTPLUG_CPU set_cpu_current_state(cpu, CPU_STATE_ONLINE); set_default_offline_state(cpu); #endif pseries_notify_cpuidle_add_cpu(cpu); }
static void smp_xics_setup_cpu(int cpu) { if (cpu != boot_cpuid) xics_setup_cpu(); if (cpu_has_feature(CPU_FTR_DBELL)) doorbell_setup_this_cpu(); if (firmware_has_feature(FW_FEATURE_SPLPAR)) vpa_init(cpu); cpumask_clear_cpu(cpu, of_spin_mask); #ifdef CONFIG_HOTPLUG_CPU set_cpu_current_state(cpu, CPU_STATE_ONLINE); set_default_offline_state(cpu); #endif }
static void smp_setup_cpu(int cpu) { if (xive_enabled()) xive_smp_setup_cpu(); else if (cpu != boot_cpuid) xics_setup_cpu(); if (firmware_has_feature(FW_FEATURE_SPLPAR)) vpa_init(cpu); cpumask_clear_cpu(cpu, of_spin_mask); #ifdef CONFIG_HOTPLUG_CPU set_cpu_current_state(cpu, CPU_STATE_ONLINE); set_default_offline_state(cpu); #endif }
static void __devinit pSeries_late_setup_cpu(int cpu) { extern unsigned int default_distrib_server; if (cur_cpu_spec->firmware_features & FW_FEATURE_SPLPAR) { vpa_init(cpu); } #ifdef CONFIG_IRQ_ALL_CPUS /* Put the calling processor into the GIQ. This is really only * necessary from a secondary thread as the OF start-cpu interface * performs this function for us on primary threads. */ /* TODO: 9005 is #defined in rtas-proc.c -- move to a header */ rtas_set_indicator(9005, default_distrib_server, 1); #endif }
static void __init pSeries_setup_arch(void) { /* Discover PIC type and setup ppc_md accordingly */ pseries_discover_pic(); /* openpic global configuration register (64-bit format). */ /* openpic Interrupt Source Unit pointer (64-bit format). */ /* python0 facility area (mmio) (64-bit format) REAL address. */ /* init to some ~sane value until calibrate_delay() runs */ loops_per_jiffy = 50000000; if (ROOT_DEV == 0) { printk("No ramdisk, default root is /dev/sda2\n"); ROOT_DEV = Root_SDA2; } fwnmi_init(); /* Find and initialize PCI host bridges */ init_pci_config_tokens(); find_and_init_phbs(); eeh_init(); pSeries_nvram_init(); /* Choose an idle loop */ if (firmware_has_feature(FW_FEATURE_SPLPAR)) { vpa_init(boot_cpuid); if (get_lppaca()->shared_proc) { printk(KERN_DEBUG "Using shared processor idle loop\n"); ppc_md.power_save = pseries_shared_idle_sleep; } else { printk(KERN_DEBUG "Using dedicated idle loop\n"); ppc_md.power_save = pseries_dedicated_idle_sleep; } } else { printk(KERN_DEBUG "Using default idle loop\n"); } if (firmware_has_feature(FW_FEATURE_LPAR)) ppc_md.enable_pmcs = pseries_lpar_enable_pmcs; else ppc_md.enable_pmcs = power4_enable_pmcs; }
/* Activate a secondary processor. */ int start_secondary(void *unused) { int cpu; cpu = current->processor; atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; smp_callin(); get_paca()->yielded = 0; if (cur_cpu_spec->firmware_features & FW_FEATURE_SPLPAR) { vpa_init(cpu); } /* Go into the idle loop. */ return cpu_idle(NULL); }
/* This is called very early */ void __init smp_init_pSeries(void) { int ret, i; DBG(" -> smp_init_pSeries()\n"); if (naca->interrupt_controller == IC_OPEN_PIC) smp_ops = &pSeries_mpic_smp_ops; else smp_ops = &pSeries_xics_smp_ops; /* Start secondary threads on SMT systems; primary threads * are already in the running state. */ for_each_present_cpu(i) { if (query_cpu_stopped(get_hard_smp_processor_id(i)) == 0) { printk("%16.16x : starting thread\n", i); DBG("%16.16x : starting thread\n", i); rtas_call(rtas_token("start-cpu"), 3, 1, &ret, get_hard_smp_processor_id(i), __pa((u32)*((unsigned long *) pseries_secondary_smp_init)), i); } } if (cur_cpu_spec->firmware_features & FW_FEATURE_SPLPAR) vpa_init(boot_cpuid); /* Non-lpar has additional take/give timebase */ if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { smp_ops->give_timebase = pSeries_give_timebase; smp_ops->take_timebase = pSeries_take_timebase; } DBG(" <- smp_init_pSeries()\n"); }
static void __init pSeries_setup_arch(void) { /* Fixup ppc_md depending on the type of interrupt controller */ if (ppc64_interrupt_controller == IC_OPEN_PIC) { ppc_md.init_IRQ = pSeries_init_mpic; ppc_md.get_irq = mpic_get_irq; ppc_md.cpu_irq_down = mpic_teardown_this_cpu; /* Allocate the mpic now, so that find_and_init_phbs() can * fill the ISUs */ pSeries_setup_mpic(); } else { ppc_md.init_IRQ = xics_init_IRQ; ppc_md.get_irq = xics_get_irq; ppc_md.cpu_irq_down = xics_teardown_cpu; } #ifdef CONFIG_SMP smp_init_pSeries(); #endif /* openpic global configuration register (64-bit format). */ /* openpic Interrupt Source Unit pointer (64-bit format). */ /* python0 facility area (mmio) (64-bit format) REAL address. */ /* init to some ~sane value until calibrate_delay() runs */ loops_per_jiffy = 50000000; if (ROOT_DEV == 0) { printk("No ramdisk, default root is /dev/sda2\n"); ROOT_DEV = Root_SDA2; } fwnmi_init(); /* Find and initialize PCI host bridges */ init_pci_config_tokens(); eeh_init(); find_and_init_phbs(); #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; #endif pSeries_nvram_init(); if (cur_cpu_spec->firmware_features & FW_FEATURE_SPLPAR) vpa_init(boot_cpuid); /* Choose an idle loop */ if (cur_cpu_spec->firmware_features & FW_FEATURE_SPLPAR) { if (get_paca()->lppaca.shared_proc) { printk(KERN_INFO "Using shared processor idle loop\n"); ppc_md.idle_loop = pseries_shared_idle; } else { printk(KERN_INFO "Using dedicated idle loop\n"); ppc_md.idle_loop = pseries_dedicated_idle; } } else { printk(KERN_INFO "Using default idle loop\n"); ppc_md.idle_loop = default_idle; } }