int ad7393_set_mode(unsigned int *option)
{
int i;
unsigned char wr_buf[AD7393_REG_NUM];
vpp_tvsys_t tvsys;
vpp_tvconn_t tvconn;
tvsys = option[0];
tvconn = option[1];
DBGMSG("set mode : tvsys %d,tvconn %d\n",tvsys,tvconn);
wr_buf[0] = 0x2;
vpp_i2c_write(AD7393_ADDR, 0x17, wr_buf, 1 ); // reset
for(i=0;i<1000;i++);
memcpy(wr_buf,AD7393_NTSC_INIT_REG,AD7393_REG_NUM);
switch(tvconn){
case VPP_TVCONN_YCBCR:
case VPP_TVCONN_YPBPR:
wr_buf[0x82] = 0xC9;
break;
case VPP_TVCONN_SCART:
case VPP_TVCONN_VGA:
wr_buf[0x02] = 0x10;
wr_buf[0x82] = 0xC9;
break;
default:
case VPP_TVCONN_SVIDEO:
case VPP_TVCONN_CVBS:
wr_buf[0x82] = 0xCB;
break;
}
if( tvsys == VPP_TVSYS_PAL ){
wr_buf[0x80] = 0x51;
wr_buf[0x82] &= ~0x8;
wr_buf[0x8c] = 0xCB;
wr_buf[0x8d] = 0x8A;
wr_buf[0x8e] = 0x09;
wr_buf[0x8f] = 0x2A;
}
vpp_i2c_write(AD7393_ADDR, 0x0, wr_buf, AD7393_REG_NUM);
return 0;
}
// return: 0 if success, otherwise failed
int cs8556_i2c_write(int addr, char data)
{
#ifdef CONFIG_KERNEL
// i2c_api_register_write(CS8556_ADDR, 2, addr, data);
vpp_i2c_write(CS8556_ID, CS8556_ADDR, addr, &data, 1);
return 0;
#else
return i2c1_write(CS8556_ADDR, addr, 2, &data, 1);
#endif
}
void ad9389_set_power_down(int enable)
{
char reg;
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,®,1);
if( enable ){
reg |= 0x40;
}
else {
reg &= ~0x40;
}
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,®,1);
}
/*----------------------- Function Body --------------------------------------*/
int ad9389_check_plugin(int hotplug)
{
unsigned char buf[1];
int plugin;
unsigned int option[2];
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x42,buf,1);
plugin = (buf[0] & BIT6)? 1:0;
printk("[AD9389] HDMI plug%s\n",(plugin)?"in":"out");
buf[0] = 0x80;
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x94,buf,1); // enable INT
buf[0] = 0x80;
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x96,buf,1); // clear HPD flag
vout_set_int_type(2); // GPIO0 3:rising edge, 2:falling edge
if( !hotplug ) return plugin;
option[0] = ad9389_colfmt;
option[1] = ad9389_dwidth;
option[1] |= (ad9389_spdif_enable)? 0x2:0x0;
if( plugin ){
do {
buf[0] = 0x10;
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,buf,1);
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,buf,1);
if((buf[0] & BIT6)==0) // Power up
break;
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x42,buf,1);
plugin = (buf[0] & BIT6)? 1:0;
if( plugin == 0 )
return 0;
} while(1);
ad9389_set_mode(&option[0]);
}
return plugin;
}
void ve_ch7305_power_on()
{
// LVDS power on
reg_t reg63;
reg63.addr = 0x63;
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data, 1);
reg63.data &= ~0x40;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data, 1);
/* add for CH7305 PLL reset to prevent CH7305 from no signal ouput */
reg_t reg76;
reg76.addr = 0x76;
reg_t reg66;
reg66.addr = 0x66;
int timeout = 0;
int ret=0;
/* wait until CH7305 PLL is stable or timeout */
while( ((ret=vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg66.addr, ®66.data, 1))>0) && !(reg66.data & 0x04) && (timeout++)<3 )
{
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg76.addr, ®76.data, 1);
reg76.data &= ~0x04;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg76.addr, ®76.data, 1);
mdelay(100);
reg76.data |= 0x04;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg76.addr, ®76.data, 1);
mdelay(100);
}
// GPIO0 and GPIO1 control backlight and power
/*REG8_VAL(GPIO_BASE_ADDR+0x80) |= 0x03;
mdelay(10);
REG8_VAL(GPIO_BASE_ADDR+0xC0) |= 0x03;
mdelay(10);*/
}
void ad7393_set_power_down(int enable)
{
char reg;
DBGMSG("power down %d\n",enable);
if( enable ){
reg = 0x3;
}
else {
reg = 0x1C;
}
vpp_i2c_write(AD7393_ADDR,0x0,®,1);
}
void ve_ch7305_power_off()
{
// GPIO0 and GPIO1 control backlight and power
/*REG8_VAL(GPIO_BASE_ADDR+0x80) &= ~0x03;
mdelay(10);
REG8_VAL(GPIO_BASE_ADDR+0xC0) &= ~0x03;
mdelay(10);*/
// LVDS power off
reg_t reg63;
reg63.addr = 0x63;
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data, 1);
reg63.data |= 0x40;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data,1);
}
int vt1632_init(struct vout_s *vo)
{
char buf[16];
vt1632_not_ready = 1;
vpp_i2c_read(VPP_DVI_I2C_ID,VT1632_ADDR, 0x0, buf, 2);
if( (buf[0] != 0x06) || (buf[1] != 0x11) ){ // check vender id
return -1;
}
vt1632_not_ready = 0;
buf[0x0] = 0x37;
buf[0x1] = 0x20;
vpp_i2c_write(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,2);
DPRINT("[VT1632] DVI ext device\n");
return 0;
}
int ad9389_config(vout_info_t *info)
{
char buf[1];
buf[0] = 0x80;
if( ad9389_colfmt == VDO_COL_FMT_YUV422H ){
switch( info->resx ){
case 1440: // 1440x480i/p, 1440x576i
buf[0] = 0xC0;
break;
default:
break;
}
}
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR, 0x3B, buf, 1);
return 0;
}
int vt1632_init(void)
{
char buf[16];
memset(buf, 0, 16);
vt1632_not_ready = 1;
vpp_i2c_read(VT1632_ADDR, 0x0, buf, 2);
if( (buf[0] != 0x06) || (buf[1] != 0x11) ){ // check vender id
DPRINT("vt1632 hw mode\n");
return -1;
}
vt1632_not_ready = 0;
buf[0x0] = 0x37;
buf[0x1] = 0x20;
vpp_i2c_write(VT1632_ADDR,0x8,buf,2);
return 0;
}
void vt1632_set_power_down(int enable)
{
char buf[1];
if( vt1632_not_ready )
return;
DBGMSG("vt1632_set_power_down(%d)\n",enable);
vpp_i2c_read(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
if( enable ){
buf[0] &= ~BIT0;
}
else {
buf[0] |= BIT0;
}
vpp_i2c_write(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
}
int vt1632_set_mode(unsigned int *option)
{
char buf[1];
vpp_datawidht_t dwidth;
if( vt1632_not_ready )
return -1;
dwidth = option[1] & BIT0;
DBGMSG("vt1632_set_mode(%d)\n",(dwidth)?24:12);
vpp_i2c_read(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
if( dwidth == VPP_DATAWIDHT_12 ){
buf[0] &= ~BIT2;
buf[0] |= BIT3;
}
else {
buf[0] |= BIT2;
buf[0] &= ~BIT3;
}
vpp_i2c_write(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
return 0;
}
static void WriteBlock(unsigned int index,char *buf,int len)
{
vpp_i2c_write(SIL902X_ADDR,index,(unsigned char *)buf,len);
}
int ad9389_set_mode(unsigned int *option)
{
vdo_color_fmt colfmt;
vpp_datawidht_t dwidth;
ad9389_output_mode_t mode;
unsigned char wr_buf[AD9389_REG_NUM];
colfmt = option[0];
dwidth = option[1] & BIT0;
ad9389_spdif_enable = ( option[1] & BIT1 )? 1:0;
ad9389_colfmt = colfmt;
ad9389_dwidth = dwidth;
switch(colfmt){
case VDO_COL_FMT_ARGB:
mode = (dwidth == VPP_DATAWIDHT_12)? AD9389_VOMODE_HDMI_RGB_12:AD9389_VOMODE_HDMI_RGB_24;
break;
case VDO_COL_FMT_YUV444:
mode = (dwidth == VPP_DATAWIDHT_12)? AD9389_VOMODE_HDMI_YUV444_12:AD9389_VOMODE_HDMI_YUV444_24;
break;
case VDO_COL_FMT_YUV422H:
mode = (dwidth == VPP_DATAWIDHT_12)? AD9389_VOMODE_MAX:AD9389_VOMODE_HDMI_YUV422_24;
break;
default:
mode = AD9389_VOMODE_MAX;
break;
}
memcpy(wr_buf,ad9389_reg_yuv444_12,AD9389_REG_NUM);
switch(mode){
case AD9389_VOMODE_HDMI_RGB_12:
DBGMSG("HDMI RGB 12bit mode\n");
wr_buf[0x15] = 0x0A;
wr_buf[0x16] = 0x02;
wr_buf[0x45] = 0x0;
// wr_buf[0x97] = 0x4;
// wr_buf[0x98] = 0x3;
// wr_buf[0xA5] = 0xC0;
wr_buf[0xAF] = 0x16;
wr_buf[0xBA] = 0xC0;
break;
case AD9389_VOMODE_HDMI_YUV444_12:
DBGMSG("HDMI YUV444 12bit mode\n");
wr_buf[0x15] = 0x0A;
wr_buf[0x16] = 0x43;
wr_buf[0x45] = 0x20;
// wr_buf[0x97] = 0x4;
// wr_buf[0x98] = 0x3;
// wr_buf[0xA5] = 0xC0;
wr_buf[0xAF] = 0x16;
wr_buf[0xBA] = 0xC0;
break;
case AD9389_VOMODE_HDMI_RGB_24:
DBGMSG("HDMI RGB 24bit mode\n");
wr_buf[0x15] = 0x0;
wr_buf[0x16] = 0x02;
wr_buf[0x45] = 0x0;
// wr_buf[0x97] = 0x4;
// wr_buf[0x98] = 0x3;
// wr_buf[0xA5] = 0xC0;
wr_buf[0xAF] = 0x16;
wr_buf[0xBA] = 0x60;
break;
case AD9389_VOMODE_HDMI_YUV444_24:
DBGMSG("HDMI YUV444 24bit mode\n");
wr_buf[0x15] = 0x0;
wr_buf[0x16] = 0x43;
wr_buf[0x45] = 0x20;
// wr_buf[0x97] = 0x4;
// wr_buf[0x98] = 0x3;
// wr_buf[0xA5] = 0xC0;
wr_buf[0xAF] = 0x16;
wr_buf[0xBA] = 0x60;
break;
case AD9389_VOMODE_HDMI_YUV422_24:
DBGMSG("HDMI YUV422 24bit mode\n");
wr_buf[0x15] = 0x02;
wr_buf[0x16] = 0xCB;
wr_buf[0x45] = 0x10;
// wr_buf[0x97] = 0x4;
// wr_buf[0x98] = 0x3;
// wr_buf[0xA5] = 0xC0;
wr_buf[0xAF] = 0x16;
wr_buf[0xBA] = 0x60;
break;
default:
DBGMSG("*E* invalid mode\n");
return -1;
}
if( ad9389_spdif_enable ){
wr_buf[0xA] |= 0x10; // 0x9 i2s, 0x19 spdif
}
wr_buf[0x94] = 0x80;
wr_buf[0x96] = 0x80;
#if 1
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR, 0x0, wr_buf, AD9389_REG_NUM);
#else
ad9389_write_reg(0x15,&wr_buf[0x15],1);
ad9389_write_reg(0x16,&wr_buf[0x16],1);
ad9389_write_reg(0x45,&wr_buf[0x45],1);
ad9389_write_reg(0x97,&wr_buf[0x97],1);
ad9389_write_reg(0x98,&wr_buf[0x98],1);
ad9389_write_reg(0xA5,&wr_buf[0xA5],1);
ad9389_write_reg(0xAF,&wr_buf[0xAF],1);
ad9389_write_reg(0xBA,&wr_buf[0xBA],1);
#endif
return 0;
}
void ve_ch7305_resume(void){
int i;
for(i = 0; i < CH7305_REG_COUNT; i++)
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, i, ®s[i], 1);
}
int ve_ch7305_set_mode(lcd_setting_t mode)
{
/* Channel and mods:
* Single channel: 800x600, 1024x768
* dual channel: 1280x1024, 1400x1050, 1600x1200
*/
reg_t pll_single[] = {
{0x6F, 0x00},
{0x70, 0x40},
{0x71, 0xED},
{0x72, 0xA3},
{0x73, 0xC8},
{0x74, 0xF6},
{0x75, 0x00},
{0x76, 0xAD},
{0x77, 0x00},
{0x78, 0x80},
{0x79, 0x02},
{0x7A, 0x00},
{0x7B, 0x00},
{0x7C, 0x30},
{0x7D, 0x02},
{0x7E, 0x00},
{0x7F, 0x10}
};
reg_t pll_dual[] = {
{0x6F, 0x00},
{0x70, 0x40},
{0x71, 0xE3},
{0x72, 0xAD},
{0x73, 0xDB},
{0x74, 0xF6},
{0x75, 0x00},
{0x76, 0x8F},
{0x77, 0x00},
{0x78, 0x80},
{0x79, 0x02},
{0x7A, 0x00},
{0x7B, 0x00},
{0x7C, 0x30},
{0x7D, 0x02},
{0x7E, 0x00},
{0x7F, 0x10}
};
// Print registers' value
// print_reg();
int i;
for (i = 0; i < 17; i++ ){
if ( mode.panel_mode & DUAL_CHANNEL )
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, pll_dual[i].addr, &pll_dual[i].data, 1);
else
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, pll_single[i].addr, &pll_single[i].data, 1);
}
reg_t reg64;
reg64.addr = 0x64;
// Input data select
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg64.addr, ®64.data, 1);
if ( mode.panel_mode & DUAL_CHANNEL )
reg64.data |= 0x10;
else
reg64.data &= ~0x10;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg64.addr, ®64.data, 1);
//Power sequence
reg_t T1,T2, T3, T4, T5;
T1.addr =0x67;
T2.addr =0x68;
T3.addr =0x69;
T4.addr =0x6A;
T5.addr =0x6B;
T1.data = 0x31;
T2.data = 0x68;
T3.data = 0x68;
T4.data = 0x31;
T5.data = 0x4;
unsigned char val;
// T1(Power On Time)
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T1.addr, &T1.data, 1);
val = T2.data & 0x80;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T2.addr, &val, 1);
// T4(Power Off Time)
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T4.addr, &T4.data, 1);
val = T3.data & 0x80;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T3.addr, &val, 1);
// T5(Power Cycle Time)
val = T5.data & 0x3F;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T5.addr, &val, 1);
// T2(Black Light Enable Time)
val = T2.data & 0x7F;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T2.addr, &val, 1);
// T3(Black Light Disable Time)
val = T3.data & 0x7F;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T3.addr, &val, 1);
// LVDS24
if ( mode.panel_mode & OUTPUT_24 )
reg64.data |= 0x20; // Output 24bits
else
reg64.data &= ~0x20; // Output 18bits
// Dithering
if ( mode.panel_mode & EN_DITHERING )
reg64.data &= ~0x08; // Enable dithering
else
reg64.data |= 0x08; // Disable dithering
// LDI
if ( mode.panel_mode & LDI)
reg64.data |= 0x1; // openLDI
else
reg64.data &= ~0x1; // SPWG
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg64.addr, ®64.data, 1);
// De-skew
reg_t reg1d;
reg1d.addr = 0x1d;
reg1d.data = 0x40;
reg1d.data |= mode.deskew_xcmd & 0xF;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg1d.addr, ®1d.data, 1);
//print registers' value
print_reg();
return 0;
}
static void WriteByte(unsigned int index,char data)
{
vpp_i2c_write(SIL902X_ADDR,index,(unsigned char *)&data,1);
}
