void
wdc_atapi_send_packet(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct scsi_xfer *sc_xfer = xfer->cmd;
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
/*
* Even with WDCS_ERR, the device should accept a command packet.
* Limit length to what can be stuffed into the cylinder register
* (16 bits). Some CD-ROMs seem to interpret '0' as 65536,
* but not all devices do that and it's not obvious from the
* ATAPI spec that this behaviour should be expected. If more
* data is necessary, multiple data transfer phases will be done.
*/
wdccommand(chp, xfer->drive, ATAPI_PKT_CMD,
xfer->c_bcount <= 0xfffe ? xfer->c_bcount : 0xfffe,
0, 0, 0,
(xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0);
if (xfer->c_flags & C_DMA)
drvp->n_xfers++;
DELAY(1);
xfer->next = wdc_atapi_intr_command;
ret->timeout = sc_xfer->timeout;
if ((drvp->atapi_cap & ATAPI_CFG_DRQ_MASK) == ATAPI_CFG_IRQ_DRQ) {
/* We expect an IRQ to tell us of the next state */
ret->expect_irq = 1;
}
WDCDEBUG_PRINT(("wdc_atapi_send_packet %s:%d:%d command sent\n",
chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive
), DEBUG_XFERS);
return;
}
void
wdc_atapi_ctrl(struct channel_softc *chp, struct wdc_xfer *xfer,
int timeout, struct atapi_return_args *ret)
{
struct scsi_xfer *sc_xfer = xfer->cmd;
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
char *errstring = NULL;
wdc_atapi_update_status(chp);
if (!timeout) {
switch (drvp->state) {
case ATAPI_IDENTIFY_WAIT_STATE:
if (chp->ch_status & WDCS_BSY)
return;
break;
default:
if (chp->ch_status & (WDCS_BSY | WDCS_DRQ))
return;
break;
}
}
if (!wdc_atapi_drive_selected(chp, xfer->drive))
{
wdc_set_drive(chp, xfer->drive);
delay (1);
}
if (timeout) {
int trigger_timeout = 1;
switch (drvp->state) {
case ATAPI_DEVICE_RESET_WAIT_STATE:
errstring = "Device Reset Wait";
drvp->drive_flags &= ~DRIVE_DEVICE_RESET;
break;
case ATAPI_IDENTIFY_WAIT_STATE:
errstring = "Identify";
if (!(chp->ch_status & WDCS_BSY) &&
(chp->ch_status & (WDCS_DRQ | WDCS_ERR)))
trigger_timeout = 0;
break;
case ATAPI_PIOMODE_STATE:
errstring = "Post-Identify";
if (!(chp->ch_status & (WDCS_BSY | WDCS_DRQ)))
trigger_timeout = 0;
break;
case ATAPI_PIOMODE_WAIT_STATE:
errstring = "PIOMODE";
if (chp->ch_status & (WDCS_BSY | WDCS_DRQ))
drvp->drive_flags &= ~DRIVE_MODE;
else
trigger_timeout = 0;
break;
case ATAPI_DMAMODE_WAIT_STATE:
errstring = "dmamode";
if (chp->ch_status & (WDCS_BSY | WDCS_DRQ))
drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
else
trigger_timeout = 0;
break;
default:
errstring = "unknown state";
break;
}
if (trigger_timeout)
goto timeout;
}
WDCDEBUG_PRINT(("wdc_atapi_ctrl %s:%d:%d state %d\n",
chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive, drvp->state),
DEBUG_INTR | DEBUG_FUNCS);
switch (drvp->state) {
/* My ATAPI slave device likes to assert DASP-/PDIAG- until
it is DEVICE RESET. This causes the LED to stay on.
There is a trade-off here. This drive will cause any
play-back or seeks happening to be interrupted.
Note that the bus reset that triggered this state
(which may have been caused by the other drive on
the chain) need not interrupt this playback. It happens
to on my Smart & Friendly CD burner.
- csapuntz@
*/
case ATAPI_RESET_BASE_STATE:
if ((drvp->drive_flags & DRIVE_DEVICE_RESET) == 0) {
drvp->state = ATAPI_IDENTIFY_STATE;
break;
}
wdccommandshort(chp, drvp->drive, ATAPI_DEVICE_RESET);
drvp->state = ATAPI_DEVICE_RESET_WAIT_STATE;
ret->delay = ATAPI_RESET_DELAY;
ret->timeout = ATAPI_RESET_WAIT;
break;
case ATAPI_DEVICE_RESET_WAIT_STATE:
/* FALLTHROUGH */
case ATAPI_IDENTIFY_STATE:
wdccommandshort(chp, drvp->drive, ATAPI_IDENTIFY_DEVICE);
drvp->state = ATAPI_IDENTIFY_WAIT_STATE;
ret->delay = 10;
ret->timeout = ATAPI_RESET_WAIT;
break;
case ATAPI_IDENTIFY_WAIT_STATE: {
int idx = 0;
while ((chp->ch_status & WDCS_DRQ) &&
idx++ < 20) {
wdcbit_bucket(chp, 512);
DELAY(1);
wdc_atapi_update_status(chp);
}
drvp->state = ATAPI_PIOMODE_STATE;
/*
* Note, we can't go directly to set PIO mode
* because the drive is free to assert BSY
* after the transfer
*/
break;
}
case ATAPI_PIOMODE_STATE:
/* Don't try to set mode if controller can't be adjusted */
if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0)
goto ready;
/* Also don't try if the drive didn't report its mode */
if ((drvp->drive_flags & DRIVE_MODE) == 0)
goto ready;
/* SET FEATURES 0x08 is only for PIO mode > 2 */
if (drvp->PIO_mode <= 2)
goto ready;
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x08 | drvp->PIO_mode, WDSF_SET_MODE);
drvp->state = ATAPI_PIOMODE_WAIT_STATE;
ret->timeout = ATAPI_CTRL_WAIT;
ret->expect_irq = 1;
break;
case ATAPI_PIOMODE_WAIT_STATE:
if (chp->wdc->cap & WDC_CAPABILITY_IRQACK)
chp->wdc->irqack(chp);
if (chp->ch_status & WDCS_ERR) {
/* Downgrade straight to PIO mode 3 */
drvp->PIO_mode = 3;
chp->wdc->set_modes(chp);
}
/* FALLTHROUGH */
case ATAPI_DMAMODE_STATE:
if (drvp->drive_flags & DRIVE_UDMA) {
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
} else if (drvp->drive_flags & DRIVE_DMA) {
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x20 | drvp->DMA_mode, WDSF_SET_MODE);
} else {
goto ready;
}
drvp->state = ATAPI_DMAMODE_WAIT_STATE;
ret->timeout = ATAPI_CTRL_WAIT;
ret->expect_irq = 1;
break;
case ATAPI_DMAMODE_WAIT_STATE:
if (chp->wdc->cap & WDC_CAPABILITY_IRQACK)
chp->wdc->irqack(chp);
if (chp->ch_status & WDCS_ERR)
drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
/* FALLTHROUGH */
case ATAPI_READY_STATE:
ready:
drvp->state = ATAPI_READY_STATE;
xfer->next = wdc_atapi_real_start;
break;
}
return;
timeout:
printf("%s:%d:%d: %s timed out\n",
chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring);
sc_xfer->error = XS_TIMEOUT;
xfer->next = wdc_atapi_reset;
return;
}
static void
wdc_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
{
struct atac_softc *atac = chp->ch_atac;
struct wdc_softc *wdc = CHAN_TO_WDC(chp);
struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
struct scsipi_xfer *sc_xfer = xfer->c_cmd;
struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive];
int wait_flags = (sc_xfer->xs_control & XS_CTL_POLL) ? AT_POLL : 0;
const char *errstring;
ATADEBUG_PRINT(("wdc_atapi_start %s:%d:%d, scsi flags 0x%x \n",
device_xname(atac->atac_dev), chp->ch_channel, drvp->drive,
sc_xfer->xs_control), DEBUG_XFERS);
#if NATA_DMA
if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER))
drvp->n_xfers++;
#endif
/* Do control operations specially. */
if (__predict_false(drvp->state < READY)) {
/* If it's not a polled command, we need the kernel thread */
if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 &&
(chp->ch_flags & ATACH_TH_RUN) == 0) {
chp->ch_queue->queue_freeze++;
wakeup(&chp->ch_thread);
return;
}
/*
* disable interrupts, all commands here should be quick
* enough to be able to poll, and we don't go here that often
*/
bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
WDCTL_4BIT | WDCTL_IDS);
if (wdc->select)
wdc->select(chp, xfer->c_drive);
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
WDSD_IBM | (xfer->c_drive << 4));
/* Don't try to set mode if controller can't be adjusted */
if (atac->atac_set_modes == NULL)
goto ready;
/* Also don't try if the drive didn't report its mode */
if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0)
goto ready;
errstring = "unbusy";
if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags))
goto timeout;
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x08 | drvp->PIO_mode, WDSF_SET_MODE);
errstring = "piomode";
if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags))
goto timeout;
if (chp->ch_status & WDCS_ERR) {
if (chp->ch_error == WDCE_ABRT) {
/*
* Some ATAPI drives reject PIO settings.
* Fall back to PIO mode 3 since that's the
* minimum for ATAPI.
*/
printf("%s:%d:%d: PIO mode %d rejected, "
"falling back to PIO mode 3\n",
device_xname(atac->atac_dev),
chp->ch_channel, xfer->c_drive,
drvp->PIO_mode);
if (drvp->PIO_mode > 3)
drvp->PIO_mode = 3;
} else
goto error;
}
#if NATA_DMA
#if NATA_UDMA
if (drvp->drive_flags & ATA_DRIVE_UDMA) {
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x40 | drvp->UDMA_mode, WDSF_SET_MODE);
} else
#endif
if (drvp->drive_flags & ATA_DRIVE_DMA) {
wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0,
0x20 | drvp->DMA_mode, WDSF_SET_MODE);
} else {
goto ready;
}
errstring = "dmamode";
if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags))
goto timeout;
if (chp->ch_status & WDCS_ERR) {
if (chp->ch_error == WDCE_ABRT) {
#if NATA_UDMA
if (drvp->drive_flags & ATA_DRIVE_UDMA)
goto error;
else
#endif
{
/*
* The drive rejected our DMA setting.
* Fall back to mode 1.
*/
printf("%s:%d:%d: DMA mode %d rejected, "
"falling back to DMA mode 0\n",
device_xname(atac->atac_dev),
chp->ch_channel, xfer->c_drive,
drvp->DMA_mode);
if (drvp->DMA_mode > 0)
drvp->DMA_mode = 0;
}
} else
goto error;
}
#endif /* NATA_DMA */
ready:
drvp->state = READY;
bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr,
WDCTL_4BIT);
delay(10); /* some drives need a little delay here */
}
/* start timeout machinery */
if ((sc_xfer->xs_control & XS_CTL_POLL) == 0)
callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
wdctimeout, chp);
if (wdc->select)
wdc->select(chp, xfer->c_drive);
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
WDSD_IBM | (xfer->c_drive << 4));
switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags)) {
case WDCWAIT_OK:
break;
case WDCWAIT_TOUT:
printf("wdc_atapi_start: not ready, st = %02x\n",
chp->ch_status);
sc_xfer->error = XS_TIMEOUT;
wdc_atapi_reset(chp, xfer);
return;
case WDCWAIT_THR:
return;
}
/*
* Even with WDCS_ERR, the device should accept a command packet
* Limit length to what can be stuffed into the cylinder register
* (16 bits). Some CD-ROMs seem to interpret '0' as 65536,
* but not all devices do that and it's not obvious from the
* ATAPI spec that that behaviour should be expected. If more
* data is necessary, multiple data transfer phases will be done.
*/
wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD,
xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff,
0, 0, 0,
#if NATA_DMA
(xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA :
#endif
0
);
#if NATA_PIOBM
if (xfer->c_flags & C_PIOBM) {
int error;
int dma_flags = (sc_xfer->xs_control & XS_CTL_DATA_IN)
? WDC_DMA_READ : 0;
if (xfer->c_flags & C_POLL) {
/* XXX not supported yet --- fall back to PIO */
xfer->c_flags &= ~C_PIOBM;
} else {
/* Init the DMA channel. */
error = (*wdc->dma_init)(wdc->dma_arg,
chp->ch_channel, xfer->c_drive,
(char *)xfer->c_databuf,
xfer->c_bcount,
dma_flags | WDC_DMA_PIOBM_ATAPI);
if (error) {
if (error == EINVAL) {
/*
* We can't do DMA on this transfer
* for some reason. Fall back to
* PIO.
*/
xfer->c_flags &= ~C_PIOBM;
error = 0;
} else {
sc_xfer->error = XS_DRIVER_STUFFUP;
errstring = "piobm";
goto error;
}
}
}
}
#endif
/*
* If there is no interrupt for CMD input, busy-wait for it (done in
* the interrupt routine. If it is a polled command, call the interrupt
* routine until command is done.
*/
if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) !=
ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) {
/* Wait for at last 400ns for status bit to be valid */
DELAY(1);
wdc_atapi_intr(chp, xfer, 0);
} else {
chp->ch_flags |= ATACH_IRQ_WAIT;
}
if (sc_xfer->xs_control & XS_CTL_POLL) {
#if NATA_DMA
if (chp->ch_flags & ATACH_DMA_WAIT) {
wdc_dmawait(chp, xfer, sc_xfer->timeout);
chp->ch_flags &= ~ATACH_DMA_WAIT;
}
#endif
while ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
/* Wait for at last 400ns for status bit to be valid */
DELAY(1);
wdc_atapi_intr(chp, xfer, 0);
}
}
return;
timeout:
printf("%s:%d:%d: %s timed out\n",
device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
errstring);
sc_xfer->error = XS_TIMEOUT;
bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
delay(10); /* some drives need a little delay here */
wdc_atapi_reset(chp, xfer);
return;
error:
printf("%s:%d:%d: %s ",
device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
errstring);
printf("error (0x%x)\n", chp->ch_error);
sc_xfer->error = XS_SHORTSENSE;
sc_xfer->sense.atapi_sense = chp->ch_error;
bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
delay(10); /* some drives need a little delay here */
wdc_atapi_reset(chp, xfer);
return;
}
