static void sparc32obsd_collect_uthread(const struct regcache *regcache, int regnum, CORE_ADDR addr) { struct gdbarch *gdbarch = get_regcache_arch (regcache); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); CORE_ADDR sp; gdb_byte buf[4]; gdb_assert (regnum >= -1); if (regnum == SPARC_SP_REGNUM || regnum == -1) { CORE_ADDR fp_addr = addr + SPARC32OBSD_UTHREAD_FP_OFFSET; regcache_raw_collect (regcache, SPARC_SP_REGNUM, buf); write_memory (fp_addr,buf, 4); } if (regnum == SPARC32_PC_REGNUM || regnum == -1) { CORE_ADDR i7, i7_addr = addr + SPARC32OBSD_UTHREAD_PC_OFFSET; regcache_raw_collect (regcache, SPARC32_PC_REGNUM, buf); i7 = extract_unsigned_integer (buf, 4, byte_order) - 8; write_memory_unsigned_integer (i7_addr, 4, byte_order, i7); if (regnum == SPARC32_PC_REGNUM) return; } regcache_raw_collect (regcache, SPARC_SP_REGNUM, buf); sp = extract_unsigned_integer (buf, 4, byte_order); sparc_collect_rwindow (regcache, sp, regnum); }
static void arm_catch_kernel_helper_return (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, struct displaced_step_closure *dsc) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); dsc->numinsns = 1; dsc->insn_addr = from; dsc->cleanup = &cleanup_kernel_helper_return; /* Say we wrote to the PC, else cleanup will set PC to the next instruction in the helper, which isn't helpful. */ dsc->wrote_to_pc = 1; /* Preparation: tmp[0] <- r14 r14 <- <scratch space>+4 *(<scratch space>+8) <- from Insn: ldr pc, [r14, #4] Cleanup: r14 <- tmp[0], pc <- tmp[0]. */ dsc->tmp[0] = displaced_read_reg (regs, dsc, ARM_LR_REGNUM); displaced_write_reg (regs, dsc, ARM_LR_REGNUM, (ULONGEST) to + 4, CANNOT_WRITE_PC); write_memory_unsigned_integer (to + 8, 4, byte_order, from); dsc->modinsn[0] = 0xe59ef004; /* ldr pc, [lr, #4]. */ }
static void sparc64obsd_collect_uthread(const struct regcache *regcache, int regnum, CORE_ADDR addr) { CORE_ADDR sp; gdb_byte buf[8]; gdb_assert (regnum >= -1); if (regnum == SPARC_SP_REGNUM || regnum == -1) { CORE_ADDR fp_addr = addr + SPARC64OBSD_UTHREAD_FP_OFFSET; regcache_raw_collect (regcache, SPARC_SP_REGNUM, buf); write_memory (fp_addr,buf, 8); } if (regnum == SPARC64_PC_REGNUM || regnum == -1) { CORE_ADDR i7, i7_addr = addr + SPARC64OBSD_UTHREAD_PC_OFFSET; regcache_raw_collect (regcache, SPARC64_PC_REGNUM, buf); i7 = extract_unsigned_integer (buf, 8) - 8; write_memory_unsigned_integer (i7_addr, 8, i7); if (regnum == SPARC64_PC_REGNUM) return; } regcache_raw_collect (regcache, SPARC_SP_REGNUM, buf); sp = extract_unsigned_integer (buf, 8); sparc_collect_rwindow (regcache, sp, regnum); }
static void amd64obsd_collect_uthread (const struct regcache *regcache, int regnum, CORE_ADDR addr) { struct gdbarch *gdbarch = get_regcache_arch (regcache); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); CORE_ADDR sp_addr = addr + AMD64OBSD_UTHREAD_RSP_OFFSET; CORE_ADDR sp = 0; gdb_byte buf[8]; int i; gdb_assert (regnum >= -1); if (regnum == -1 || regnum == AMD64_RSP_REGNUM) { int offset; /* Calculate the stack pointer (frame pointer) that will be stored into the thread structure. */ offset = amd64obsd_uthread_reg_offset[AMD64_RIP_REGNUM] + 8; regcache_raw_collect (regcache, AMD64_RSP_REGNUM, buf); sp = extract_unsigned_integer (buf, 8, byte_order) - offset; /* Store the stack pointer. */ write_memory_unsigned_integer (sp_addr, 8, byte_order, sp); /* The stack pointer was (potentially) modified. Make sure we build a proper stack frame. */ regnum = -1; } for (i = 0; i < ARRAY_SIZE (amd64obsd_uthread_reg_offset); i++) { if (amd64obsd_uthread_reg_offset[i] != -1 && (regnum == -1 || regnum == i)) { /* Fetch stack pointer from thread structure (if we didn't calculate it already). */ if (sp == 0) sp = read_memory_unsigned_integer (sp_addr, 8, byte_order); /* Write the register into the stack frame. */ regcache_raw_collect (regcache, i, buf); write_memory (sp + amd64obsd_uthread_reg_offset[i], buf, 8); } } }
static CORE_ADDR mn10300_push_dummy_call (struct gdbarch *gdbarch, struct value *target_func, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) { const int push_size = register_size (gdbarch, E_PC_REGNUM); int regs_used; int len, arg_len; int stack_offset = 0; int argnum; char *val, valbuf[MAX_REGISTER_SIZE]; /* This should be a nop, but align the stack just in case something went wrong. Stacks are four byte aligned on the mn10300. */ sp &= ~3; /* Now make space on the stack for the args. XXX This doesn't appear to handle pass-by-invisible reference arguments. */ regs_used = struct_return ? 1 : 0; for (len = 0, argnum = 0; argnum < nargs; argnum++) { arg_len = (TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3; while (regs_used < 2 && arg_len > 0) { regs_used++; arg_len -= push_size; } len += arg_len; } /* Allocate stack space. */ sp -= len; if (struct_return) { regs_used = 1; write_register (E_D0_REGNUM, struct_addr); } else regs_used = 0; /* Push all arguments onto the stack. */ for (argnum = 0; argnum < nargs; argnum++) { /* FIXME what about structs? Unions? */ if (TYPE_CODE (value_type (*args)) == TYPE_CODE_STRUCT && TYPE_LENGTH (value_type (*args)) > 8) { /* Change to pointer-to-type. */ arg_len = push_size; store_unsigned_integer (valbuf, push_size, VALUE_ADDRESS (*args)); val = &valbuf[0]; } else { arg_len = TYPE_LENGTH (value_type (*args)); val = (char *) value_contents (*args); } while (regs_used < 2 && arg_len > 0) { write_register (regs_used, extract_unsigned_integer (val, push_size)); val += push_size; arg_len -= push_size; regs_used++; } while (arg_len > 0) { write_memory (sp + stack_offset, val, push_size); arg_len -= push_size; val += push_size; stack_offset += push_size; } args++; } /* Make space for the flushback area. */ sp -= 8; /* Push the return address that contains the magic breakpoint. */ sp -= 4; write_memory_unsigned_integer (sp, push_size, bp_addr); /* Update $sp. */ regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp); return sp; }
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) { CORE_ADDR func_addr = find_function_addr (function, NULL); struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); /* By this stage in the proceedings, SP has been decremented by "red zone size" + "struct return size". Fetch the stack-pointer from before this and use that as the BACK_CHAIN. */ const CORE_ADDR back_chain = read_sp (); /* See for-loop comment below. */ int write_pass; /* Size of the Altivec's vector parameter region, the final value is computed in the for-loop below. */ LONGEST vparam_size = 0; /* Size of the general parameter region, the final value is computed in the for-loop below. */ LONGEST gparam_size = 0; /* Kevin writes ... I don't mind seeing tdep->wordsize used in the calls to align_up(), align_down(), etc. because this makes it easier to reuse this code (in a copy/paste sense) in the future, but it is a 64-bit ABI and asserting that the wordsize is 8 bytes at some point makes it easier to verify that this function is correct without having to do a non-local analysis to figure out the possible values of tdep->wordsize. */ gdb_assert (tdep->wordsize == 8); /* Go through the argument list twice. Pass 1: Compute the function call's stack space and register requirements. Pass 2: Replay the same computation but this time also write the values out to the target. */ for (write_pass = 0; write_pass < 2; write_pass++) { int argno; /* Next available floating point register for float and double arguments. */ int freg = 1; /* Next available general register for non-vector (but possibly float) arguments. */ int greg = 3; /* Next available vector register for vector arguments. */ int vreg = 2; /* The address, at which the next general purpose parameter (integer, struct, float, ...) should be saved. */ CORE_ADDR gparam; /* Address, at which the next Altivec vector parameter should be saved. */ CORE_ADDR vparam; if (!write_pass) { /* During the first pass, GPARAM and VPARAM are more like offsets (start address zero) than addresses. That way the accumulate the total stack space each region requires. */ gparam = 0; vparam = 0; } else { /* Decrement the stack pointer making space for the Altivec and general on-stack parameters. Set vparam and gparam to their corresponding regions. */ vparam = align_down (sp - vparam_size, 16); gparam = align_down (vparam - gparam_size, 16); /* Add in space for the TOC, link editor double word, compiler double word, LR save area, CR save area. */ sp = align_down (gparam - 48, 16); } /* If the function is returning a `struct', then there is an extra hidden parameter (which will be passed in r3) containing the address of that struct.. In that case we should advance one word and start from r4 register to copy parameters. This also consumes one on-stack parameter slot. */ if (struct_return) { if (write_pass) regcache_cooked_write_signed (regcache, tdep->ppc_gp0_regnum + greg, struct_addr); greg++; gparam = align_up (gparam + tdep->wordsize, tdep->wordsize); } for (argno = 0; argno < nargs; argno++) { struct value *arg = args[argno]; struct type *type = check_typedef (value_type (arg)); const bfd_byte *val = value_contents (arg); if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8) { /* Floats and Doubles go in f1 .. f13. They also consume a left aligned GREG,, and can end up in memory. */ if (write_pass) { if (ppc_floating_point_unit_p (current_gdbarch) && freg <= 13) { gdb_byte regval[MAX_REGISTER_SIZE]; struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); convert_typed_floating (val, type, regval, regtype); regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + freg, regval); } if (greg <= 10) { /* The ABI states "Single precision floating point values are mapped to the first word in a single doubleword" and "... floating point values mapped to the first eight doublewords of the parameter save area are also passed in general registers"). This code interprets that to mean: store it, left aligned, in the general register. */ gdb_byte regval[MAX_REGISTER_SIZE]; memset (regval, 0, sizeof regval); memcpy (regval, val, TYPE_LENGTH (type)); regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + greg, regval); } write_memory (gparam, val, TYPE_LENGTH (type)); } /* Always consume parameter stack space. */ freg++; greg++; gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize); } else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type) && TYPE_CODE (type) == TYPE_CODE_ARRAY && tdep->ppc_vr0_regnum >= 0) { /* In the Altivec ABI, vectors go in the vector registers v2 .. v13, or when that runs out, a vector annex which goes above all the normal parameters. NOTE: cagney/2003-09-21: This is a guess based on the PowerOpen Altivec ABI. */ if (vreg <= 13) { if (write_pass) regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + vreg, val); vreg++; } else { if (write_pass) write_memory (vparam, val, TYPE_LENGTH (type)); vparam = align_up (vparam + TYPE_LENGTH (type), 16); } } else if ((TYPE_CODE (type) == TYPE_CODE_INT || TYPE_CODE (type) == TYPE_CODE_ENUM || TYPE_CODE (type) == TYPE_CODE_PTR) && TYPE_LENGTH (type) <= 8) { /* Scalars and Pointers get sign[un]extended and go in gpr3 .. gpr10. They can also end up in memory. */ if (write_pass) { /* Sign extend the value, then store it unsigned. */ ULONGEST word = unpack_long (type, val); /* Convert any function code addresses into descriptors. */ if (TYPE_CODE (type) == TYPE_CODE_PTR && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC) { CORE_ADDR desc = word; convert_code_addr_to_desc_addr (word, &desc); word = desc; } if (greg <= 10) regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + greg, word); write_memory_unsigned_integer (gparam, tdep->wordsize, word); } greg++; gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize); } else { int byte; for (byte = 0; byte < TYPE_LENGTH (type); byte += tdep->wordsize) { if (write_pass && greg <= 10) { gdb_byte regval[MAX_REGISTER_SIZE]; int len = TYPE_LENGTH (type) - byte; if (len > tdep->wordsize) len = tdep->wordsize; memset (regval, 0, sizeof regval); /* WARNING: cagney/2003-09-21: As best I can tell, the ABI specifies that the value should be left aligned. Unfortunately, GCC doesn't do this - it instead right aligns even sized values and puts odd sized values on the stack. Work around that by putting both a left and right aligned value into the register (hopefully no one notices :-^). Arrrgh! */ /* Left aligned (8 byte values such as pointers fill the buffer). */ memcpy (regval, val + byte, len); /* Right aligned (but only if even). */ if (len == 1 || len == 2 || len == 4) memcpy (regval + tdep->wordsize - len, val + byte, len); regcache_cooked_write (regcache, greg, regval); } greg++; } if (write_pass) /* WARNING: cagney/2003-09-21: Strictly speaking, this isn't necessary, unfortunately, GCC appears to get "struct convention" parameter passing wrong putting odd sized structures in memory instead of in a register. Work around this by always writing the value to memory. Fortunately, doing this simplifies the code. */ write_memory (gparam, val, TYPE_LENGTH (type)); if (write_pass) /* WARNING: cagney/2004-06-20: It appears that GCC likes to put structures containing a single floating-point member in an FP register instead of general general purpose. */ /* Always consume parameter stack space. */ gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize); } } if (!write_pass) { /* Save the true region sizes ready for the second pass. */ vparam_size = vparam; /* Make certain that the general parameter save area is at least the minimum 8 registers (or doublewords) in size. */ if (greg < 8) gparam_size = 8 * tdep->wordsize; else gparam_size = gparam; } } /* Update %sp. */ regcache_cooked_write_signed (regcache, SP_REGNUM, sp); /* Write the backchain (it occupies WORDSIZED bytes). */ write_memory_signed_integer (sp, tdep->wordsize, back_chain); /* Point the inferior function call's return address at the dummy's breakpoint. */ regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); /* Use the func_addr to find the descriptor, and use that to find the TOC. */ { CORE_ADDR desc_addr; if (convert_code_addr_to_desc_addr (func_addr, &desc_addr)) { /* The TOC is the second double word in the descriptor. */ CORE_ADDR toc = read_memory_unsigned_integer (desc_addr + tdep->wordsize, tdep->wordsize); regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 2, toc); } } return sp; }
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) { CORE_ADDR func_addr = find_function_addr (function, NULL); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); ULONGEST back_chain; /* See for-loop comment below. */ int write_pass; /* Size of the Altivec's vector parameter region, the final value is computed in the for-loop below. */ LONGEST vparam_size = 0; /* Size of the general parameter region, the final value is computed in the for-loop below. */ LONGEST gparam_size = 0; /* Kevin writes ... I don't mind seeing tdep->wordsize used in the calls to align_up(), align_down(), etc. because this makes it easier to reuse this code (in a copy/paste sense) in the future, but it is a 64-bit ABI and asserting that the wordsize is 8 bytes at some point makes it easier to verify that this function is correct without having to do a non-local analysis to figure out the possible values of tdep->wordsize. */ gdb_assert (tdep->wordsize == 8); /* This function exists to support a calling convention that requires floating-point registers. It shouldn't be used on processors that lack them. */ gdb_assert (ppc_floating_point_unit_p (gdbarch)); /* By this stage in the proceedings, SP has been decremented by "red zone size" + "struct return size". Fetch the stack-pointer from before this and use that as the BACK_CHAIN. */ regcache_cooked_read_unsigned (regcache, gdbarch_sp_regnum (gdbarch), &back_chain); /* Go through the argument list twice. Pass 1: Compute the function call's stack space and register requirements. Pass 2: Replay the same computation but this time also write the values out to the target. */ for (write_pass = 0; write_pass < 2; write_pass++) { int argno; /* Next available floating point register for float and double arguments. */ int freg = 1; /* Next available general register for non-vector (but possibly float) arguments. */ int greg = 3; /* Next available vector register for vector arguments. */ int vreg = 2; /* The address, at which the next general purpose parameter (integer, struct, float, ...) should be saved. */ CORE_ADDR gparam; /* Address, at which the next Altivec vector parameter should be saved. */ CORE_ADDR vparam; if (!write_pass) { /* During the first pass, GPARAM and VPARAM are more like offsets (start address zero) than addresses. That way they accumulate the total stack space each region requires. */ gparam = 0; vparam = 0; } else { /* Decrement the stack pointer making space for the Altivec and general on-stack parameters. Set vparam and gparam to their corresponding regions. */ vparam = align_down (sp - vparam_size, 16); gparam = align_down (vparam - gparam_size, 16); /* Add in space for the TOC, link editor double word, compiler double word, LR save area, CR save area. */ sp = align_down (gparam - 48, 16); } /* If the function is returning a `struct', then there is an extra hidden parameter (which will be passed in r3) containing the address of that struct.. In that case we should advance one word and start from r4 register to copy parameters. This also consumes one on-stack parameter slot. */ if (struct_return) { if (write_pass) regcache_cooked_write_signed (regcache, tdep->ppc_gp0_regnum + greg, struct_addr); greg++; gparam = align_up (gparam + tdep->wordsize, tdep->wordsize); } for (argno = 0; argno < nargs; argno++) { struct value *arg = args[argno]; struct type *type = check_typedef (value_type (arg)); const bfd_byte *val = value_contents (arg); if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8) { /* Floats and Doubles go in f1 .. f13. They also consume a left aligned GREG,, and can end up in memory. */ if (write_pass) { gdb_byte regval[MAX_REGISTER_SIZE]; const gdb_byte *p; /* Version 1.7 of the 64-bit PowerPC ELF ABI says: "Single precision floating point values are mapped to the first word in a single doubleword." And version 1.9 says: "Single precision floating point values are mapped to the second word in a single doubleword." GDB then writes single precision floating point values at both words in a doubleword, to support both ABIs. */ if (TYPE_LENGTH (type) == 4) { memcpy (regval, val, 4); memcpy (regval + 4, val, 4); p = regval; } else p = val; /* Write value in the stack's parameter save area. */ write_memory (gparam, p, 8); if (freg <= 13) { struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); convert_typed_floating (val, type, regval, regtype); regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + freg, regval); } if (greg <= 10) regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + greg, regval); } freg++; greg++; /* Always consume parameter stack space. */ gparam = align_up (gparam + 8, tdep->wordsize); } else if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 16 && (gdbarch_long_double_format (gdbarch) == floatformats_ibm_long_double)) { /* IBM long double stored in two doublewords of the parameter save area and corresponding registers. */ if (write_pass) { if (!tdep->soft_float && freg <= 13) { regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + freg, val); if (freg <= 12) regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + freg + 1, val + 8); } if (greg <= 10) { regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + greg, val); if (greg <= 9) regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + greg + 1, val + 8); } write_memory (gparam, val, TYPE_LENGTH (type)); } freg += 2; greg += 2; gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize); } else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) <= 8) { /* 32-bit and 64-bit decimal floats go in f1 .. f13. They can end up in memory. */ if (write_pass) { gdb_byte regval[MAX_REGISTER_SIZE]; const gdb_byte *p; /* 32-bit decimal floats are right aligned in the doubleword. */ if (TYPE_LENGTH (type) == 4) { memcpy (regval + 4, val, 4); p = regval; } else p = val; /* Write value in the stack's parameter save area. */ write_memory (gparam, p, 8); if (freg <= 13) regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + freg, p); } freg++; greg++; /* Always consume parameter stack space. */ gparam = align_up (gparam + 8, tdep->wordsize); } else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16) { /* 128-bit decimal floats go in f2 .. f12, always in even/odd pairs. They can end up in memory, using two doublewords. */ if (write_pass) { if (freg <= 12) { /* Make sure freg is even. */ freg += freg & 1; regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + freg, val); regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + freg + 1, val + 8); } write_memory (gparam, val, TYPE_LENGTH (type)); } freg += 2; greg += 2; gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize); } else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type) && TYPE_CODE (type) == TYPE_CODE_ARRAY && tdep->ppc_vr0_regnum >= 0) { /* In the Altivec ABI, vectors go in the vector registers v2 .. v13, or when that runs out, a vector annex which goes above all the normal parameters. NOTE: cagney/2003-09-21: This is a guess based on the PowerOpen Altivec ABI. */ if (vreg <= 13) { if (write_pass) regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + vreg, val); vreg++; } else { if (write_pass) write_memory (vparam, val, TYPE_LENGTH (type)); vparam = align_up (vparam + TYPE_LENGTH (type), 16); } } else if ((TYPE_CODE (type) == TYPE_CODE_INT || TYPE_CODE (type) == TYPE_CODE_ENUM || TYPE_CODE (type) == TYPE_CODE_BOOL || TYPE_CODE (type) == TYPE_CODE_CHAR || TYPE_CODE (type) == TYPE_CODE_PTR || TYPE_CODE (type) == TYPE_CODE_REF) && TYPE_LENGTH (type) <= 8) { /* Scalars and Pointers get sign[un]extended and go in gpr3 .. gpr10. They can also end up in memory. */ if (write_pass) { /* Sign extend the value, then store it unsigned. */ ULONGEST word = unpack_long (type, val); /* Convert any function code addresses into descriptors. */ if (TYPE_CODE (type) == TYPE_CODE_PTR || TYPE_CODE (type) == TYPE_CODE_REF) { struct type *target_type; target_type = check_typedef (TYPE_TARGET_TYPE (type)); if (TYPE_CODE (target_type) == TYPE_CODE_FUNC || TYPE_CODE (target_type) == TYPE_CODE_METHOD) { CORE_ADDR desc = word; convert_code_addr_to_desc_addr (word, &desc); word = desc; } } if (greg <= 10) regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + greg, word); write_memory_unsigned_integer (gparam, tdep->wordsize, byte_order, word); } greg++; gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize); } else { int byte; for (byte = 0; byte < TYPE_LENGTH (type); byte += tdep->wordsize) { if (write_pass && greg <= 10) { gdb_byte regval[MAX_REGISTER_SIZE]; int len = TYPE_LENGTH (type) - byte; if (len > tdep->wordsize) len = tdep->wordsize; memset (regval, 0, sizeof regval); /* The ABI (version 1.9) specifies that values smaller than one doubleword are right-aligned and those larger are left-aligned. GCC versions before 3.4 implemented this incorrectly; see <http://gcc.gnu.org/gcc-3.4/powerpc-abi.html>. */ if (byte == 0) memcpy (regval + tdep->wordsize - len, val + byte, len); else memcpy (regval, val + byte, len); regcache_cooked_write (regcache, greg, regval); } greg++; } if (write_pass) { /* WARNING: cagney/2003-09-21: Strictly speaking, this isn't necessary, unfortunately, GCC appears to get "struct convention" parameter passing wrong putting odd sized structures in memory instead of in a register. Work around this by always writing the value to memory. Fortunately, doing this simplifies the code. */ int len = TYPE_LENGTH (type); if (len < tdep->wordsize) write_memory (gparam + tdep->wordsize - len, val, len); else write_memory (gparam, val, len); } if (freg <= 13 && TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1 && TYPE_LENGTH (type) <= 16) { /* The ABI (version 1.9) specifies that structs containing a single floating-point value, at any level of nesting of single-member structs, are passed in floating-point registers. */ while (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) type = check_typedef (TYPE_FIELD_TYPE (type, 0)); if (TYPE_CODE (type) == TYPE_CODE_FLT) { if (TYPE_LENGTH (type) <= 8) { if (write_pass) { gdb_byte regval[MAX_REGISTER_SIZE]; struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); convert_typed_floating (val, type, regval, regtype); regcache_cooked_write (regcache, (tdep->ppc_fp0_regnum + freg), regval); } freg++; } else if (TYPE_LENGTH (type) == 16 && (gdbarch_long_double_format (gdbarch) == floatformats_ibm_long_double)) { if (write_pass) { regcache_cooked_write (regcache, (tdep->ppc_fp0_regnum + freg), val); if (freg <= 12) regcache_cooked_write (regcache, (tdep->ppc_fp0_regnum + freg + 1), val + 8); } freg += 2; } } } /* Always consume parameter stack space. */ gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize); } } if (!write_pass) { /* Save the true region sizes ready for the second pass. */ vparam_size = vparam; /* Make certain that the general parameter save area is at least the minimum 8 registers (or doublewords) in size. */ if (greg < 8) gparam_size = 8 * tdep->wordsize; else gparam_size = gparam; } } /* Update %sp. */ regcache_cooked_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp); /* Write the backchain (it occupies WORDSIZED bytes). */ write_memory_signed_integer (sp, tdep->wordsize, byte_order, back_chain); /* Point the inferior function call's return address at the dummy's breakpoint. */ regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); /* Use the func_addr to find the descriptor, and use that to find the TOC. If we're calling via a function pointer, the pointer itself identifies the descriptor. */ { struct type *ftype = check_typedef (value_type (function)); CORE_ADDR desc_addr = value_as_address (function); if (TYPE_CODE (ftype) == TYPE_CODE_PTR || convert_code_addr_to_desc_addr (func_addr, &desc_addr)) { /* The TOC is the second double word in the descriptor. */ CORE_ADDR toc = read_memory_unsigned_integer (desc_addr + tdep->wordsize, tdep->wordsize, byte_order); regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 2, toc); } } return sp; }
static CORE_ADDR lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int first_arg_reg = SIM_LM32_R1_REGNUM; int num_arg_regs = 8; int i; /* Set the return address. */ regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr); /* If we're returning a large struct, a pointer to the address to store it at is passed as a first hidden parameter. */ if (struct_return) { regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr); first_arg_reg++; num_arg_regs--; sp -= 4; } /* Setup parameters. */ for (i = 0; i < nargs; i++) { struct value *arg = args[i]; struct type *arg_type = check_typedef (value_type (arg)); gdb_byte *contents; ULONGEST val; /* Promote small integer types to int. */ switch (TYPE_CODE (arg_type)) { case TYPE_CODE_INT: case TYPE_CODE_BOOL: case TYPE_CODE_CHAR: case TYPE_CODE_RANGE: case TYPE_CODE_ENUM: if (TYPE_LENGTH (arg_type) < 4) { arg_type = builtin_type (gdbarch)->builtin_int32; arg = value_cast (arg_type, arg); } break; } /* FIXME: Handle structures. */ contents = (gdb_byte *) value_contents (arg); val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type), byte_order); /* First num_arg_regs parameters are passed by registers, and the rest are passed on the stack. */ if (i < num_arg_regs) regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val); else { write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order, val); sp -= 4; } } /* Update stack pointer. */ regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp); /* Return adjusted stack pointer. */ return sp; }