/* * Disable the PHY interrupt */ static void disable_phyirq(struct net_device *dev) { struct at91_private *lp = netdev_priv(dev); unsigned int dsintr; unsigned int irq_number; irq_number = lp->board_data.phy_irq_pin; if (!irq_number) { del_timer_sync(&lp->check_timer); return; } spin_lock_irq(&lp->lock); enable_mdi(); if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); dsintr = dsintr | 0xf00; /* set bits 8..11 */ write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); } else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); } else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); dsintr = ~(1 << 14); write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); } else if ((lp->phy_type == MII_KS8721_ID) || (lp->phy_type == MII_KSZ8041_ID)) { /* for Micrel PHY */ read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); dsintr = ~((1 << 10) | (1 << 8)); write_phy(lp->phy_address, MII_TPISTATUS, dsintr); } else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); } else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); } else if (lp->phy_type == MII_STE100P_ID) { /* for STE100P PHY */ read_phy(lp->phy_address, MII_STE100P_XIE_REG, &dsintr); dsintr = dsintr & ~0x7f; write_phy(lp->phy_address, MII_STE100P_XIE_REG, dsintr); } disable_mdi(); spin_unlock_irq(&lp->lock); free_irq(irq_number, dev); /* Free interrupt handler */ }
/* * Initialize and enable the PHY interrupt for link-state changes */ static void enable_phyirq(struct net_device *dev) { struct at91_private *lp = (struct at91_private *) dev->priv; unsigned int dsintr, irq_number; int status; irq_number = lp->board_data.phy_irq_pin; if (!irq_number) { /* * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), * or board does not have it connected. */ check_timer.expires = jiffies + LINK_POLL_INTERVAL; add_timer(&check_timer); return; } status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); if (status) { printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); return; } spin_lock_irq(&lp->lock); enable_mdi(); if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); } else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); } else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ dsintr = (1 << 15) | ( 1 << 14); write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); } else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ dsintr = (1 << 10) | ( 1 << 8); write_phy(lp->phy_address, MII_TPISTATUS, dsintr); } disable_mdi(); spin_unlock_irq(&lp->lock); }
void ethernet_initialize(uint8_t mac[6]) { //Conf the LEDs write_phy(PHLCON, 0b0011110000010011); //Configure some buffers and MAC stuff for half duplex //Recieve buffer spans 0x0000 to 0x0FFF switch_bank(0); spi_transaction(WRITE_CONTROL_REGISTER, ERXSTL, 0x00); spi_transaction(WRITE_CONTROL_REGISTER, ERXSTH, 0x00); spi_transaction(WRITE_CONTROL_REGISTER, ERXNDL, 0xFF); spi_transaction(WRITE_CONTROL_REGISTER, ERXNDH, 0x0F); spi_transaction(WRITE_CONTROL_REGISTER, ERXRDPTL, 0x00); spi_transaction(WRITE_CONTROL_REGISTER, ERXRDPTH, 0x00); //Transmit buffers covers 0x1000 to 0x1FFF //... uint8_t reg; do { reg = spi_transaction(READ_CONTROL_REGISTER, ESTAT, 0); } while(!(reg & (1<<CLKRDY))); //MAC settings switch_bank(2); spi_transaction(WRITE_CONTROL_REGISTER, MACON1, (1<<MARXEN)); spi_transaction(WRITE_CONTROL_REGISTER, MACON3, 0b11110000); spi_transaction(WRITE_CONTROL_REGISTER, MACON4, 0b01000000); //DEFER //1518 bytes spi_transaction(WRITE_CONTROL_REGISTER, MAMXFLL, 0xEE); spi_transaction(WRITE_CONTROL_REGISTER, MAMXFLH, 0x05); spi_transaction(WRITE_CONTROL_REGISTER, MABBIPG, 0x12); spi_transaction(WRITE_CONTROL_REGISTER, MAIPGL, 0x12); spi_transaction(WRITE_CONTROL_REGISTER, MAIPGH, 0x0C); set_mac(mac); write_phy(PHCON2, (1<<HDLDIS)); write_phy(PHCON1, 0); //Enable reception spi_transaction(BIT_FIELD_SET, ECON1, (1<<RXEN)); puts("Enabled reception"); }
/* * Initialize and enable the PHY interrupt for link-state changes */ static void enable_phyirq(struct net_device *dev) { struct at91_private *lp = netdev_priv(dev); unsigned int dsintr, irq_number; int status; irq_number = lp->board_data.phy_irq_pin; if (!irq_number) { /* * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), * or board does not have it connected. */ mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); return; } status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); if (status) { ; return; } spin_lock_irq(&lp->lock); enable_mdi(); if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); } else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); } else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ dsintr = (1 << 15) | ( 1 << 14); write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); } else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ dsintr = (1 << 10) | ( 1 << 8); write_phy(lp->phy_address, MII_TPISTATUS, dsintr); } else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); dsintr = dsintr | 0x500; /* set bits 8, 10 */ write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); } else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); dsintr = dsintr | 0x3c; /* set bits 2..5 */ write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); dsintr = dsintr | 0x3; /* set bits 0,1 */ write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); } disable_mdi(); spin_unlock_irq(&lp->lock); }
/* * Initialize and enable the PHY interrupt for link-state changes */ static void enable_phyirq(struct net_device *dev) { struct at91_private *lp = (struct at91_private *) dev->priv; unsigned int dsintr, irq_number; int status; if (lp->phy_type == MII_RTL8201_ID) /* RTL8201 does not have an interrupt */ return; if (lp->phy_type == MII_DP83847_ID) /* DP83847 does not have an interrupt */ return; if (lp->phy_type == MII_AC101L_ID) /* AC101L interrupt not supported yet */ return; irq_number = lp->board_data.phy_irq_pin; status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); if (status) { printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); return; } spin_lock_irq(&lp->lock); enable_mdi(); if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); } else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); } else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ dsintr = (1 << 15) | ( 1 << 14); write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); } else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ dsintr = (1 << 10) | ( 1 << 8); write_phy(lp->phy_address, MII_TPISTATUS, dsintr); } disable_mdi(); spin_unlock_irq(&lp->lock); }
/* * Disable the PHY interrupt */ static void disable_phyirq(struct net_device *dev) { struct at91_private *lp = (struct at91_private *) dev->priv; unsigned int dsintr; unsigned int irq_number; if (lp->phy_type == MII_RTL8201_ID) /* RTL8201 does not have an interrupt */ return; if (lp->phy_type == MII_DP83847_ID) /* DP83847 does not have an interrupt */ return; if (lp->phy_type == MII_AC101L_ID) /* AC101L interrupt not supported yet */ return; spin_lock_irq(&lp->lock); enable_mdi(); if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); dsintr = dsintr | 0xf00; /* set bits 8..11 */ write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); } else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); } else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); dsintr = ~(1 << 14); write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); } else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); dsintr = ~((1 << 10) | (1 << 8)); write_phy(lp->phy_address, MII_TPISTATUS, dsintr); } disable_mdi(); spin_unlock_irq(&lp->lock); irq_number = lp->board_data.phy_irq_pin; free_irq(irq_number, dev); /* Free interrupt handler */ }
static void enable_phyirq(struct net_device *dev) { struct at91_private *lp = netdev_priv(dev); unsigned int dsintr, irq_number; int status; irq_number = lp->board_data.phy_irq_pin; if (!irq_number) { mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); return; } status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); if (status) { printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); return; } spin_lock_irq(&lp->lock); enable_mdi(); if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); dsintr = dsintr & ~0xf00; write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); } else if (lp->phy_type == MII_LXT971A_ID) { read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); dsintr = dsintr | 0xf2; write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); } else if (lp->phy_type == MII_BCM5221_ID) { dsintr = (1 << 15) | ( 1 << 14); write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); } else if (lp->phy_type == MII_KS8721_ID) { dsintr = (1 << 10) | ( 1 << 8); write_phy(lp->phy_address, MII_TPISTATUS, dsintr); } else if (lp->phy_type == MII_T78Q21x3_ID) { read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); dsintr = dsintr | 0x500; write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); } else if (lp->phy_type == MII_DP83848_ID) { read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); dsintr = dsintr | 0x3c; write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); dsintr = dsintr | 0x3; write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); } disable_mdi(); spin_unlock_irq(&lp->lock); }
static void disable_phyirq(struct net_device *dev) { struct at91_private *lp = netdev_priv(dev); unsigned int dsintr; unsigned int irq_number; irq_number = lp->board_data.phy_irq_pin; if (!irq_number) { del_timer_sync(&lp->check_timer); return; } spin_lock_irq(&lp->lock); enable_mdi(); if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); dsintr = dsintr | 0xf00; write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); } else if (lp->phy_type == MII_LXT971A_ID) { read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); dsintr = dsintr & ~0xf2; write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); } else if (lp->phy_type == MII_BCM5221_ID) { read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); dsintr = ~(1 << 14); write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); } else if (lp->phy_type == MII_KS8721_ID) { read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); dsintr = ~((1 << 10) | (1 << 8)); write_phy(lp->phy_address, MII_TPISTATUS, dsintr); } else if (lp->phy_type == MII_T78Q21x3_ID) { read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); dsintr = dsintr & ~0x500; write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); } else if (lp->phy_type == MII_DP83848_ID) { read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); dsintr = dsintr & ~0x3; write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); dsintr = dsintr & ~0x3c; write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); } disable_mdi(); spin_unlock_irq(&lp->lock); free_irq(irq_number, dev); }
static void reset_phy(struct net_device *dev) { struct at91_private *lp = netdev_priv(dev); unsigned int bmcr; spin_lock_irq(&lp->lock); enable_mdi(); /* Perform PHY reset */ write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); /* Wait until PHY reset is complete */ do { read_phy(lp->phy_address, MII_BMCR, &bmcr); } while (!(bmcr & BMCR_RESET)); disable_mdi(); spin_unlock_irq(&lp->lock); }
static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag) { unsigned int dsintr; enable_mdi(); mask_irq(28); sep_emac_write(MAC_INTMASK,0x0); //首先屏蔽中断 sepether_start(); /* Enable PHY interrupt */ *(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ; //1 stands for in *(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ; //for common use *(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080; //中断输入方式 *(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14); //中断类型为低电平解发 *(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080; //清除中断 *(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000; //清除中断 rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL); enable_irq(INTSRC_EXINT7); read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr); dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr); update_link_speed(dm9161_device.phy_addr); /************************************************************************************/ /* Enable MAC interrupts */ sep_emac_write(MAC_INTMASK,0xff); //open中断 sep_emac_write(MAC_INTSRC,0xff); //clear all mac irq unmask_irq(28); disable_mdi(); rt_kprintf("SEP4020 ethernet interface open!\n\r"); return RT_EOK; }
void pcie_phy_init(struct msm_pcie_dev_t *dev) { PCIE_DBG(dev, "RC%d: Initializing 28nm ATE phy - 100MHz\n", dev->rc_idx); /* 1 */ write_phy(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0x01); /* 2 */ write_phy(dev->phy, QSERDES_COM_SYS_CLK_CTRL, 0x3e); /* 3 */ write_phy(dev->phy, QSERDES_COM_PLL_CP_SETI, 0x0f); /* 4 */ write_phy(dev->phy, QSERDES_COM_PLL_IP_SETP, 0x23); /* 5 */ write_phy(dev->phy, QSERDES_COM_PLL_IP_SETI, 0x3f); /* 6 */ write_phy(dev->phy, QSERDES_RX_CDR_CONTROL, 0xf3); /* 7 */ write_phy(dev->phy, QSERDES_RX_CDR_CONTROL2, 0x6b); /* 8 */ write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x10); /* 9 */ write_phy(dev->phy, QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE, 0x87); /* 10 */ write_phy(dev->phy, QSERDES_RX_RX_EQ_GAIN12, 0x54); /* 11 */ write_phy(dev->phy, PCIE_PHY_POWER_STATE_CONFIG1, 0xa3); /* 12 */ write_phy(dev->phy, PCIE_PHY_POWER_STATE_CONFIG2, 0x1b); /* 13 */ write_phy(dev->phy, PCIE_PHY_SW_RESET, 0x00); /* 14 */ write_phy(dev->phy, PCIE_PHY_START, 0x03); }
void pcie_phy_init(struct msm_pcie_dev_t *dev) { PCIE_DBG(dev, "RC%d: Initializing 20nm QMP phy - 19.2MHz\n", dev->rc_idx); write_phy(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0x03); write_phy(dev->phy, QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08); write_phy(dev->phy, QSERDES_COM_DEC_START1, 0x82); write_phy(dev->phy, QSERDES_COM_DEC_START2, 0x03); write_phy(dev->phy, QSERDES_COM_DIV_FRAC_START1, 0xD5); write_phy(dev->phy, QSERDES_COM_DIV_FRAC_START2, 0xAA); write_phy(dev->phy, QSERDES_COM_DIV_FRAC_START3, 0x4D); write_phy(dev->phy, QSERDES_COM_PLLLOCK_CMP_EN, 0x01); write_phy(dev->phy, QSERDES_COM_PLLLOCK_CMP1, 0x2B); write_phy(dev->phy, QSERDES_COM_PLLLOCK_CMP2, 0x68); write_phy(dev->phy, QSERDES_COM_PLL_CRCTRL, 0x7C); write_phy(dev->phy, QSERDES_COM_PLL_CP_SETI, 0x02); write_phy(dev->phy, QSERDES_COM_PLL_IP_SETP, 0x1F); write_phy(dev->phy, QSERDES_COM_PLL_CP_SETP, 0x0F); write_phy(dev->phy, QSERDES_COM_PLL_IP_SETI, 0x01); write_phy(dev->phy, QSERDES_COM_IE_TRIM, 0x0F); write_phy(dev->phy, QSERDES_COM_IP_TRIM, 0x0F); write_phy(dev->phy, QSERDES_COM_PLL_CNTRL, 0x46); /* CDR Settings */ write_phy(dev->phy, QSERDES_RX_CDR_CONTROL1, 0xF3); write_phy(dev->phy, QSERDES_RX_CDR_CONTROL_HALF, 0x2B); /* Calibration Settings */ write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x90); write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL2, 0x05); /* Additional writes */ write_phy(dev->phy, QSERDES_COM_RES_CODE_START_SEG1, 0x20); write_phy(dev->phy, QSERDES_COM_RES_CODE_CAL_CSR, 0x77); write_phy(dev->phy, QSERDES_COM_RES_TRIM_CONTROL, 0x15); write_phy(dev->phy, QSERDES_TX_RCV_DETECT_LVL, 0x03); write_phy(dev->phy, QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF); write_phy(dev->phy, QSERDES_RX_RX_EQ_GAIN1_MSB, 0x1F); write_phy(dev->phy, QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF); write_phy(dev->phy, QSERDES_RX_RX_EQ_GAIN2_MSB, 0x00); write_phy(dev->phy, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1A); write_phy(dev->phy, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x80); write_phy(dev->phy, QSERDES_RX_SIGDET_ENABLES, 0x40); write_phy(dev->phy, QSERDES_RX_SIGDET_CNTRL, 0x70); write_phy(dev->phy, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x06); write_phy(dev->phy, QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10); write_phy(dev->phy, PCIE_PHY_ENDPOINT_REFCLK_DRIVE, 0x10); write_phy(dev->phy, PCIE_PHY_POWER_STATE_CONFIG1, 0x23); write_phy(dev->phy, PCIE_PHY_POWER_STATE_CONFIG2, 0xCB); write_phy(dev->phy, QSERDES_RX_RX_RCVR_IQ_EN, 0x31); write_phy(dev->phy, PCIE_PHY_SW_RESET, 0x00); write_phy(dev->phy, PCIE_PHY_START, 0x03); }
void pcie_phy_dump(struct msm_pcie_dev_t *dev) { int i; int control_offset[2] = {0x60, 0x70}; PCIE_DBG(dev, "RC%d\n", dev->rc_idx); for (i = 0; i < 2; i++) { write_phy(dev->phy, PCIE_PHY_TEST_CONTROL, control_offset[i]); PCIE_REG(dev, "RC%d: TEST_CONTROL: 0x%08x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_TEST_CONTROL)); PCIE_REG(dev, "RC%d: DEBUG_BUS_0_STATUS: 0x%08x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_0_STATUS)); PCIE_REG(dev, "RC%d: DEBUG_BUS_1_STATUS: 0x%08x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_1_STATUS)); PCIE_REG(dev, "RC%d: DEBUG_BUS_2_STATUS: 0x%08x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_2_STATUS)); PCIE_REG(dev, "RC%d: DEBUG_BUS_3_STATUS: 0x%08x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_3_STATUS)); } PCIE_REG(dev, "RC%d QSERDES_COM_PLL_VCO_HIGH: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_PLL_VCO_HIGH)); PCIE_REG(dev, "RC%d QSERDES_COM_RESET_SM: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_RESET_SM)); PCIE_REG(dev, "RC%d QSERDES_RX_PI_CTRL1: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_PI_CTRL1)); PCIE_REG(dev, "RC%d QSERDES_RX_PI_CTRL2: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_PI_CTRL2)); PCIE_REG(dev, "RC%d QSERDES_RX_PI_QUAD: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_PI_QUAD)); PCIE_REG(dev, "RC%d QSERDES_RX_IDATA1: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDATA1)); PCIE_REG(dev, "RC%d QSERDES_RX_IDATA2: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDATA2)); PCIE_REG(dev, "RC%d QSERDES_RX_AUX_DATA1: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AUX_DATA1)); PCIE_REG(dev, "RC%d QSERDES_RX_AUX_DATA2: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AUX_DATA2)); PCIE_REG(dev, "RC%d QSERDES_RX_AC_JTAG_OUTP: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AC_JTAG_OUTP)); PCIE_REG(dev, "RC%d QSERDES_RX_AC_JTAG_OUTN: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AC_JTAG_OUTN)); PCIE_REG(dev, "RC%d QSERDES_TX_BIST_STATUS: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_BIST_STATUS)); PCIE_REG(dev, "RC%d QSERDES_TX_BIST_ERROR_COUNT1: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_BIST_ERROR_COUNT1)); PCIE_REG(dev, "RC%d QSERDES_TX_BIST_ERROR_COUNT2: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_BIST_ERROR_COUNT2)); PCIE_REG(dev, "RC%d PCIE_PHY_BIST_CHK_ERR_CNT_L: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_BIST_CHK_ERR_CNT_L)); PCIE_REG(dev, "RC%d PCIE_PHY_BIST_CHK_ERR_CNT_H: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_BIST_CHK_ERR_CNT_H)); PCIE_REG(dev, "RC%d PCIE_PHY_BIST_CHK_STATUS: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_BIST_CHK_STATUS)); PCIE_REG(dev, "RC%d PCIE_PHY_PCS_STATUS: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_PCS_STATUS)); PCIE_REG(dev, "RC%d PCIE_PHY_REVISION_ID0: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID0)); PCIE_REG(dev, "RC%d PCIE_PHY_REVISION_ID1: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID1)); PCIE_REG(dev, "RC%d PCIE_PHY_REVISION_ID2: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID2)); PCIE_REG(dev, "RC%d PCIE_PHY_REVISION_ID3: 0x%x\n", dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID3)); }
void pcie_phy_init(struct msm_pcie_dev_t *dev) { PCIE_DBG(dev, "RC%d: Initializing 28nm QMP phy - 19.2MHz\n", dev->rc_idx); write_phy(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0x03); write_phy(dev->phy, QSERDES_COM_SYSCLK_EN_SEL, 0x08); write_phy(dev->phy, QSERDES_COM_DEC_START1, 0x82); write_phy(dev->phy, QSERDES_COM_DEC_START2, 0x03); write_phy(dev->phy, QSERDES_COM_DIV_FRAC_START1, 0xd5); write_phy(dev->phy, QSERDES_COM_DIV_FRAC_START2, 0xaa); write_phy(dev->phy, QSERDES_COM_DIV_FRAC_START3, 0x13); write_phy(dev->phy, QSERDES_COM_PLLLOCK_CMP_EN, 0x01); write_phy(dev->phy, QSERDES_COM_PLLLOCK_CMP1, 0x2b); write_phy(dev->phy, QSERDES_COM_PLLLOCK_CMP2, 0x68); write_phy(dev->phy, QSERDES_COM_PLL_CRCTRL, 0xff); write_phy(dev->phy, QSERDES_COM_PLL_CP_SETI, 0x3f); write_phy(dev->phy, QSERDES_COM_PLL_IP_SETP, 0x07); write_phy(dev->phy, QSERDES_COM_PLL_CP_SETP, 0x03); if(dev->rc_idx == 1) { write_phy(dev->phy, QSERDES_TX_TX_EMP_POST1_LVL, 0x21); write_phy(dev->phy, QSERDES_TX_TX_DRV_LVL, 0x18); } write_phy(dev->phy, QSERDES_RX_CDR_CONTROL, 0xf3); write_phy(dev->phy, QSERDES_RX_CDR_CONTROL2, 0x6b); write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x10); write_phy(dev->phy, QSERDES_RX_RX_TERM_HIGHZ_CM_AC_COUPLE, 0x87); write_phy(dev->phy, QSERDES_RX_RX_EQ_GAIN12, 0x54); write_phy(dev->phy, PCIE_PHY_POWER_STATE_CONFIG1, 0xa3); write_phy(dev->phy, PCIE_PHY_POWER_STATE_CONFIG2, 0x4b); if(dev->rc_idx == 0) { write_phy(dev->phy, QSERDES_RX_SIGDET_CNTRL, 0x50); } write_phy(dev->phy, QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10); write_phy(dev->phy, PCIE_PHY_ENDPOINT_REFCLK_DRIVE, 0x10); write_phy(dev->phy, PCIE_PHY_SW_RESET, 0x00); write_phy(dev->phy, PCIE_PHY_START, 0x03); }