void rtl8225_set_gain(struct net_device *dev, short gain) { write_phy_ofdm(dev, 0x0d, rtl8225_gain[gain * 4]); write_phy_ofdm(dev, 0x23, rtl8225_gain[gain * 4 + 1]); write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 4 + 2]); write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 4 + 3]); }
// // Description: // Change Antenna Switch. // bool SetAntenna8185( struct net_device *dev, u8 u1bAntennaIndex ) { struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); bool bAntennaSwitched = false; // printk("+SetAntenna8185(): Antenna is switching to: %d \n", u1bAntennaIndex); switch(u1bAntennaIndex) { case 0: /* Mac register, main antenna */ write_nic_byte(dev, ANTSEL, 0x03); /* base band */ write_phy_cck(dev, 0x11, 0x9b); /* Config CCK RX antenna. */ write_phy_ofdm(dev, 0x0d, 0x5c); /* Config OFDM RX antenna. */ bAntennaSwitched = true; break; case 1: /* Mac register, aux antenna */ write_nic_byte(dev, ANTSEL, 0x00); /* base band */ write_phy_cck(dev, 0x11, 0xbb); /* Config CCK RX antenna. */ write_phy_ofdm(dev, 0x0d, 0x54); /* Config OFDM RX antenna. */ bAntennaSwitched = true; break; default: printk("SetAntenna8185: unknown u1bAntennaIndex(%d)\n", u1bAntennaIndex); break; } if(bAntennaSwitched) { priv->CurrAntennaIndex = u1bAntennaIndex; } // printk("-SetAntenna8185(): return (%#X)\n", bAntennaSwitched); return bAntennaSwitched; }
void rtl8225z2_set_gain(struct net_device *dev, short gain) { const u8 *rtl8225_gain; struct r8180_priv *priv = ieee80211_priv(dev); u8 mode = priv->ieee80211->mode; if (mode == IEEE_B || mode == IEEE_G) rtl8225_gain = rtl8225z2_gain_bg; else rtl8225_gain = rtl8225z2_gain_a; write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]); write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]); write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]); write_phy_ofdm(dev, 0x21, 0x37); }
bool SetAntenna8185(struct net_device *dev, u8 u1bAntennaIndex) { struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev); bool bAntennaSwitched = false; switch (u1bAntennaIndex) { case 0: write_nic_byte(dev, ANTSEL, 0x03); write_phy_cck(dev, 0x11, 0x9b); write_phy_ofdm(dev, 0x0d, 0x5c); bAntennaSwitched = true; break; case 1: write_nic_byte(dev, ANTSEL, 0x00); write_phy_cck(dev, 0x11, 0xbb); write_phy_ofdm(dev, 0x0d, 0x54); bAntennaSwitched = true; break; default: printk("SetAntenna8185: unknown u1bAntennaIndex(%d)\n", u1bAntennaIndex); break; } if(bAntennaSwitched) priv->CurrAntennaIndex = u1bAntennaIndex; return bAntennaSwitched; }
/* switch between mode B and G */ void rtl8225_set_mode(struct net_device *dev, short modeb) { write_phy_ofdm(dev, 0x15, (modeb ? 0x0 : 0x40)); write_phy_ofdm(dev, 0x17, (modeb ? 0x0 : 0x40)); }
void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch) { struct r8180_priv *priv = ieee80211_priv(dev); int GainIdx; int GainSetting; int i; u8 power; u8 *cck_power_table; u8 max_cck_power_level; u8 max_ofdm_power_level; u8 min_ofdm_power_level; u8 cck_power_level = 0xff & priv->chtxpwr[ch]; u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch]; if(priv->card_type == USB){ max_cck_power_level = 11; max_ofdm_power_level = 25; // 12 -> 25 min_ofdm_power_level = 10; }else{ max_cck_power_level = 35; max_ofdm_power_level = 35; min_ofdm_power_level = 0; } /* CCK power setting */ if(cck_power_level > max_cck_power_level) cck_power_level = max_cck_power_level; GainIdx=cck_power_level % 6; GainSetting=cck_power_level / 6; if(ch == 14) cck_power_table = rtl8225_tx_power_cck_ch14; else cck_power_table = rtl8225_tx_power_cck; // if(priv->card_8185 == 1 && priv->card_8185_Bversion ){ /*Ver B*/ // write_nic_byte(dev, TX_GAIN_CCK, rtl8225_tx_gain_cck_ofdm[GainSetting]); // }else{ /*Ver C - D */ write_nic_byte(dev, TX_GAIN_CCK, rtl8225_tx_gain_cck_ofdm[GainSetting]>>1); // } for(i=0;i<8;i++){ power = cck_power_table[GainIdx * 8 + i]; write_phy_cck(dev, 0x44 + i, power); } /* FIXME Is this delay really needeed ? */ force_pci_posting(dev); mdelay(1); /* OFDM power setting */ // Old: // if(ofdm_power_level > max_ofdm_power_level) // ofdm_power_level = 35; // ofdm_power_level += min_ofdm_power_level; // Latest: if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level)) ofdm_power_level = max_ofdm_power_level; else ofdm_power_level += min_ofdm_power_level; if(ofdm_power_level > 35) ofdm_power_level = 35; // GainIdx=ofdm_power_level % 6; GainSetting=ofdm_power_level / 6; #if 1 // if(priv->card_type == USB){ rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON); write_phy_ofdm(dev,2,0x42); write_phy_ofdm(dev,6,0); write_phy_ofdm(dev,8,0); // } #endif // if(priv->card_8185 == 1 && priv->card_8185_Bversion){ // /*Ver B*/ // write_nic_byte(dev, TX_GAIN_OFDM, rtl8225_tx_gain_cck_ofdm[GainSetting]); // }else{ /*Ver C - D */ write_nic_byte(dev, TX_GAIN_OFDM, rtl8225_tx_gain_cck_ofdm[GainSetting]>>1); // } power = rtl8225_tx_power_ofdm[GainIdx]; write_phy_ofdm(dev, 0x5, power); write_phy_ofdm(dev, 0x7, power); force_pci_posting(dev); mdelay(1); //write_nic_byte(dev, TX_AGC_CONTROL,4); }
void rtl8225_set_gain(struct net_device *dev, short gain) { struct r8180_priv *priv = ieee80211_priv(dev); rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON); if(priv->card_8185 == 2) write_phy_ofdm(dev, 0x21, 0x27); else write_phy_ofdm(dev, 0x21, 0x37); write_phy_ofdm(dev, 0x25, 0x20); write_phy_ofdm(dev, 0x11, 0x6); if(priv->card_8185 == 1 && priv->card_8185_Bversion) write_phy_ofdm(dev, 0x27, 0x8); else write_phy_ofdm(dev, 0x27, 0x88); write_phy_ofdm(dev, 0x14, 0); write_phy_ofdm(dev, 0x16, 0); write_phy_ofdm(dev, 0x15, 0x40); write_phy_ofdm(dev, 0x17, 0x40); write_phy_ofdm(dev, 0x0d, rtl8225_gain[gain * 4]); write_phy_ofdm(dev, 0x23, rtl8225_gain[gain * 4 + 1]); write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 4 + 2]); write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 4 + 3]); //rtl8225_set_gain_usb(dev, gain); }
bool SetZebraRFPowerState8185(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState) { struct r8180_priv *priv = ieee80211_priv(dev); u8 btCR9346, btConfig3; bool bActionAllowed = true, bTurnOffBB = true; u8 u1bTmp; int i; bool bResult = true; u8 QueueID; if (priv->SetRFPowerStateInProgress == true) return false; priv->SetRFPowerStateInProgress = true; btCR9346 = read_nic_byte(dev, CR9346); write_nic_byte(dev, CR9346, (btCR9346 | 0xC0)); btConfig3 = read_nic_byte(dev, CONFIG3); write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En)); switch (eRFPowerState) { case eRfOn: write_nic_word(dev, 0x37C, 0x00EC); /* turn on AFE */ write_nic_byte(dev, 0x54, 0x00); write_nic_byte(dev, 0x62, 0x00); /* turn on RF */ RF_WriteReg(dev, 0x0, 0x009f); udelay(500); RF_WriteReg(dev, 0x4, 0x0972); udelay(500); /* turn on RF again */ RF_WriteReg(dev, 0x0, 0x009f); udelay(500); RF_WriteReg(dev, 0x4, 0x0972); udelay(500); /* turn on BB */ write_phy_ofdm(dev, 0x10, 0x40); write_phy_ofdm(dev, 0x12, 0x40); /* Avoid power down at init time. */ write_nic_byte(dev, CONFIG4, priv->RFProgType); u1bTmp = read_nic_byte(dev, 0x24E); write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6)))); break; case eRfSleep: for (QueueID = 0, i = 0; QueueID < 6;) { if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) { QueueID++; continue; } else { priv->TxPollingTimes++; if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) { bActionAllowed = false; break; } else udelay(10); } } if (bActionAllowed) { /* turn off BB RXIQ matrix to cut off rx signal */ write_phy_ofdm(dev, 0x10, 0x00); write_phy_ofdm(dev, 0x12, 0x00); /* turn off RF */ RF_WriteReg(dev, 0x4, 0x0000); RF_WriteReg(dev, 0x0, 0x0000); /* turn off AFE except PLL */ write_nic_byte(dev, 0x62, 0xff); write_nic_byte(dev, 0x54, 0xec); mdelay(1); { int i = 0; while (true) { u8 tmp24F = read_nic_byte(dev, 0x24f); if ((tmp24F == 0x01) || (tmp24F == 0x09)) { bTurnOffBB = true; break; } else { udelay(10); i++; priv->TxPollingTimes++; if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) { bTurnOffBB = false; break; } else udelay(10); } } } if (bTurnOffBB) { /* turn off BB */ u1bTmp = read_nic_byte(dev, 0x24E); write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); /* turn off AFE PLL */ write_nic_byte(dev, 0x54, 0xFC); write_nic_word(dev, 0x37C, 0x00FC); } } break; case eRfOff: for (QueueID = 0, i = 0; QueueID < 6;) { if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) { QueueID++; continue; } else { udelay(10); i++; } if (i >= MAX_DOZE_WAITING_TIMES_85B) break; } /* turn off BB RXIQ matrix to cut off rx signal */ write_phy_ofdm(dev, 0x10, 0x00); write_phy_ofdm(dev, 0x12, 0x00); /* turn off RF */ RF_WriteReg(dev, 0x4, 0x0000); RF_WriteReg(dev, 0x0, 0x0000); /* turn off AFE except PLL */ write_nic_byte(dev, 0x62, 0xff); write_nic_byte(dev, 0x54, 0xec); mdelay(1); { int i = 0; while (true) { u8 tmp24F = read_nic_byte(dev, 0x24f); if ((tmp24F == 0x01) || (tmp24F == 0x09)) { bTurnOffBB = true; break; } else { bTurnOffBB = false; udelay(10); i++; } if (i > MAX_POLLING_24F_TIMES_87SE) break; } } if (bTurnOffBB) { /* turn off BB */ u1bTmp = read_nic_byte(dev, 0x24E); write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6)); /* turn off AFE PLL (80M) */ write_nic_byte(dev, 0x54, 0xFC); write_nic_word(dev, 0x37C, 0x00FC); } break; } btConfig3 &= ~(CONFIG3_PARM_En); write_nic_byte(dev, CONFIG3, btConfig3); btCR9346 &= ~(0xC0); write_nic_byte(dev, CR9346, btCR9346); if (bResult && bActionAllowed) priv->eRFPowerState = eRFPowerState; priv->SetRFPowerStateInProgress = false; return bResult && bActionAllowed; }
void rtl8225z2_rf_set_mode(struct net_device *dev) { struct r8180_priv *priv = ieee80211_priv(dev); if (priv->ieee80211->mode == IEEE_A) { write_rtl8225(dev, 0x5, 0x1865); write_nic_dword(dev, RF_PARA, 0x10084); write_nic_dword(dev, RF_TIMING, 0xa8008); write_phy_ofdm(dev, 0x0, 0x0); write_phy_ofdm(dev, 0xa, 0x6); write_phy_ofdm(dev, 0xb, 0x99); write_phy_ofdm(dev, 0xf, 0x20); write_phy_ofdm(dev, 0x11, 0x7); rtl8225z2_set_gain(dev, 4); write_phy_ofdm(dev, 0x15, 0x40); write_phy_ofdm(dev, 0x17, 0x40); write_nic_dword(dev, 0x94, 0x10000000); } else { write_rtl8225(dev, 0x5, 0x1864); write_nic_dword(dev, RF_PARA, 0x10044); write_nic_dword(dev, RF_TIMING, 0xa8008); write_phy_ofdm(dev, 0x0, 0x1); write_phy_ofdm(dev, 0xa, 0x6); write_phy_ofdm(dev, 0xb, 0x99); write_phy_ofdm(dev, 0xf, 0x20); write_phy_ofdm(dev, 0x11, 0x7); rtl8225z2_set_gain(dev, 4); write_phy_ofdm(dev, 0x15, 0x40); write_phy_ofdm(dev, 0x17, 0x40); write_nic_dword(dev, 0x94, 0x04000002); } }
void rtl8225z2_rf_init(struct net_device *dev) { struct r8180_priv *priv = ieee80211_priv(dev); int i; short channel = 1; u16 brsr; u32 data, addr; priv->chan = channel; rtl8225_host_pci_init(dev); write_nic_dword(dev, RF_TIMING, 0x000a8008); brsr = read_nic_word(dev, BRSR); write_nic_word(dev, BRSR, 0xffff); write_nic_dword(dev, RF_PARA, 0x100044); rtl8180_set_mode(dev, EPROM_CMD_CONFIG); write_nic_byte(dev, CONFIG3, 0x44); rtl8180_set_mode(dev, EPROM_CMD_NORMAL); rtl8185_rf_pins_enable(dev); write_rtl8225(dev, 0x0, 0x2bf); mdelay(1); write_rtl8225(dev, 0x1, 0xee0); mdelay(1); write_rtl8225(dev, 0x2, 0x44d); mdelay(1); write_rtl8225(dev, 0x3, 0x441); mdelay(1); write_rtl8225(dev, 0x4, 0x8c3); mdelay(1); write_rtl8225(dev, 0x5, 0xc72); mdelay(1); write_rtl8225(dev, 0x6, 0xe6); mdelay(1); write_rtl8225(dev, 0x7, rtl8225_chan[channel]); mdelay(1); write_rtl8225(dev, 0x8, 0x3f); mdelay(1); write_rtl8225(dev, 0x9, 0x335); mdelay(1); write_rtl8225(dev, 0xa, 0x9d4); mdelay(1); write_rtl8225(dev, 0xb, 0x7bb); mdelay(1); write_rtl8225(dev, 0xc, 0x850); mdelay(1); write_rtl8225(dev, 0xd, 0xcdf); mdelay(1); write_rtl8225(dev, 0xe, 0x2b); mdelay(1); write_rtl8225(dev, 0xf, 0x114); mdelay(100); write_rtl8225(dev, 0x0, 0x1b7); for (i = 0; i < 95; i++) { write_rtl8225(dev, 0x1, (u8)(i + 1)); write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]); } write_rtl8225(dev, 0x3, 0x80); write_rtl8225(dev, 0x5, 0x4); write_rtl8225(dev, 0x0, 0xb7); write_rtl8225(dev, 0x2, 0xc4d); /* FIXME!! rtl8187 we have to check if calibrarion * is successful and eventually cal. again (repeat * the two write on reg 2) */ data = read_rtl8225(dev, 6); if (!(data & 0x00000080)) { write_rtl8225(dev, 0x02, 0x0c4d); force_pci_posting(dev); mdelay(200); write_rtl8225(dev, 0x02, 0x044d); force_pci_posting(dev); mdelay(100); data = read_rtl8225(dev, 6); if (!(data & 0x00000080)) DMESGW("RF Calibration Failed!!!!\n"); } mdelay(200); write_rtl8225(dev, 0x0, 0x2bf); for (i = 0; i < 128; i++) { data = rtl8225_agc[i]; addr = i + 0x80; /* enable writing AGC table */ write_phy_ofdm(dev, 0xb, data); mdelay(1); write_phy_ofdm(dev, 0xa, addr); mdelay(1); } force_pci_posting(dev); mdelay(1); write_phy_ofdm(dev, 0x00, 0x01); mdelay(1); write_phy_ofdm(dev, 0x01, 0x02); mdelay(1); write_phy_ofdm(dev, 0x02, 0x62); mdelay(1); write_phy_ofdm(dev, 0x03, 0x00); mdelay(1); write_phy_ofdm(dev, 0x04, 0x00); mdelay(1); write_phy_ofdm(dev, 0x05, 0x00); mdelay(1); write_phy_ofdm(dev, 0x06, 0x40); mdelay(1); write_phy_ofdm(dev, 0x07, 0x00); mdelay(1); write_phy_ofdm(dev, 0x08, 0x40); mdelay(1); write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1); write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1); write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1); write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1); write_phy_ofdm(dev, 0x0d, 0x43); write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1); write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1); write_phy_ofdm(dev, 0x10, 0x84); mdelay(1); write_phy_ofdm(dev, 0x11, 0x07); mdelay(1); write_phy_ofdm(dev, 0x12, 0x20); mdelay(1); write_phy_ofdm(dev, 0x13, 0x20); mdelay(1); write_phy_ofdm(dev, 0x14, 0x00); mdelay(1); write_phy_ofdm(dev, 0x15, 0x40); mdelay(1); write_phy_ofdm(dev, 0x16, 0x00); mdelay(1); write_phy_ofdm(dev, 0x17, 0x40); mdelay(1); write_phy_ofdm(dev, 0x18, 0xef); mdelay(1); write_phy_ofdm(dev, 0x19, 0x19); mdelay(1); write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1); write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1); write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1); write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1); write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1); write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1); write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1); write_phy_ofdm(dev, 0x21, 0x17); mdelay(1); write_phy_ofdm(dev, 0x22, 0x16); mdelay(1); write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */ write_phy_ofdm(dev, 0x24, 0x46); mdelay(1); write_phy_ofdm(dev, 0x25, 0x00); mdelay(1); write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); write_phy_ofdm(dev, 0x27, 0x88); mdelay(1); rtl8225z2_set_gain(dev, 4); write_phy_cck(dev, 0x0, 0x98); mdelay(1); write_phy_cck(dev, 0x3, 0x20); mdelay(1); write_phy_cck(dev, 0x4, 0x7e); mdelay(1); write_phy_cck(dev, 0x5, 0x12); mdelay(1); write_phy_cck(dev, 0x6, 0xfc); mdelay(1); write_phy_cck(dev, 0x7, 0x78); mdelay(1); write_phy_cck(dev, 0x8, 0x2e); mdelay(1); write_phy_cck(dev, 0x10, 0x93); mdelay(1); write_phy_cck(dev, 0x11, 0x88); mdelay(1); write_phy_cck(dev, 0x12, 0x47); mdelay(1); write_phy_cck(dev, 0x13, 0xd0); write_phy_cck(dev, 0x19, 0x00); write_phy_cck(dev, 0x1a, 0xa0); write_phy_cck(dev, 0x1b, 0x08); write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */ write_phy_cck(dev, 0x41, 0x8d); mdelay(1); write_phy_cck(dev, 0x42, 0x15); mdelay(1); write_phy_cck(dev, 0x43, 0x18); mdelay(1); write_phy_cck(dev, 0x44, 0x36); mdelay(1); write_phy_cck(dev, 0x45, 0x35); mdelay(1); write_phy_cck(dev, 0x46, 0x2e); mdelay(1); write_phy_cck(dev, 0x47, 0x25); mdelay(1); write_phy_cck(dev, 0x48, 0x1c); mdelay(1); write_phy_cck(dev, 0x49, 0x12); mdelay(1); write_phy_cck(dev, 0x4a, 0x09); mdelay(1); write_phy_cck(dev, 0x4b, 0x04); mdelay(1); write_phy_cck(dev, 0x4c, 0x05); mdelay(1); write_nic_byte(dev, 0x5b, 0x0d); mdelay(1); rtl8225z2_SetTXPowerLevel(dev, channel); /* RX antenna default to A */ write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* B: 0xDB */ write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* B: 0x10 */ rtl8185_tx_antenna(dev, 0x03); /* B: 0x00 */ /* switch to high-speed 3-wire * last digit. 2 for both cck and ofdm */ write_nic_dword(dev, 0x94, 0x15c00002); rtl8185_rf_pins_enable(dev); rtl8225_rf_set_chan(dev, priv->chan); }
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch) { struct r8180_priv *priv = ieee80211_priv(dev); u8 max_cck_power_level; u8 max_ofdm_power_level; u8 min_ofdm_power_level; char cck_power_level = (char)(0xff & priv->chtxpwr[ch]); char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]); if (IS_DOT11D_ENABLE(priv->ieee80211) && IS_DOT11D_STATE_DONE(priv->ieee80211)) { u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch); u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm); u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm); if (cck_power_level > CckMaxPwrIdx) cck_power_level = CckMaxPwrIdx; if (ofdm_power_level > OfdmMaxPwrIdx) ofdm_power_level = OfdmMaxPwrIdx; } max_cck_power_level = 15; max_ofdm_power_level = 25; min_ofdm_power_level = 10; if (cck_power_level > 35) cck_power_level = 35; write_nic_byte(dev, CCK_TXAGC, (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level])); force_pci_posting(dev); mdelay(1); if (ofdm_power_level > 35) ofdm_power_level = 35; if (priv->up == 0) { write_phy_ofdm(dev, 2, 0x42); write_phy_ofdm(dev, 5, 0x00); write_phy_ofdm(dev, 6, 0x40); write_phy_ofdm(dev, 7, 0x00); write_phy_ofdm(dev, 8, 0x40); } write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]); if (ofdm_power_level <= 11) { write_phy_ofdm(dev, 0x07, 0x5c); write_phy_ofdm(dev, 0x09, 0x5c); } if (ofdm_power_level <= 17) { write_phy_ofdm(dev, 0x07, 0x54); write_phy_ofdm(dev, 0x09, 0x54); } else { write_phy_ofdm(dev, 0x07, 0x50); write_phy_ofdm(dev, 0x09, 0x50); } force_pci_posting(dev); mdelay(1); }
static void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch) { struct r8180_priv *priv = ieee80211_priv(dev); int GainIdx; int GainSetting; int i; u8 power; const u8 *cck_power_table; u8 max_cck_power_level; u8 max_ofdm_power_level; u8 min_ofdm_power_level; u8 cck_power_level = 0xff & priv->chtxpwr[ch]; u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch]; max_cck_power_level = 35; max_ofdm_power_level = 35; min_ofdm_power_level = 0; if (cck_power_level > max_cck_power_level) cck_power_level = max_cck_power_level; GainIdx = cck_power_level % 6; GainSetting = cck_power_level / 6; if (ch == 14) cck_power_table = rtl8225_tx_power_cck_ch14; else cck_power_table = rtl8225_tx_power_cck; write_nic_byte(dev, TX_GAIN_CCK, rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1); for (i = 0; i < 8; i++) { power = cck_power_table[GainIdx * 8 + i]; write_phy_cck(dev, 0x44 + i, power); } /* FIXME Is this delay really needeed ? */ force_pci_posting(dev); mdelay(1); if (ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level)) ofdm_power_level = max_ofdm_power_level; else ofdm_power_level += min_ofdm_power_level; if (ofdm_power_level > 35) ofdm_power_level = 35; GainIdx = ofdm_power_level % 6; GainSetting = ofdm_power_level / 6; rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON); write_phy_ofdm(dev, 2, 0x42); write_phy_ofdm(dev, 6, 0x00); write_phy_ofdm(dev, 8, 0x00); write_nic_byte(dev, TX_GAIN_OFDM, rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1); power = rtl8225_tx_power_ofdm[GainIdx]; write_phy_ofdm(dev, 5, power); write_phy_ofdm(dev, 7, power); force_pci_posting(dev); mdelay(1); }
void rtl8225z2_rf_init(struct net_device *dev) { struct r8180_priv *priv = ieee80211_priv(dev); int i; short channel = 1; u16 brsr; u32 data,addr; priv->chan = channel; rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON); if(priv->card_type == USB) rtl8225_host_usb_init(dev); else rtl8225_host_pci_init(dev); write_nic_dword(dev, RF_TIMING, 0x000a8008); brsr = read_nic_word(dev, BRSR); write_nic_word(dev, BRSR, 0xffff); write_nic_dword(dev, RF_PARA, 0x100044); #if 1 //0->1 rtl8180_set_mode(dev, EPROM_CMD_CONFIG); write_nic_byte(dev, CONFIG3, 0x44); rtl8180_set_mode(dev, EPROM_CMD_NORMAL); #endif rtl8185_rf_pins_enable(dev); // mdelay(1000); write_rtl8225(dev, 0x0, 0x2bf); mdelay(1); write_rtl8225(dev, 0x1, 0xee0); mdelay(1); write_rtl8225(dev, 0x2, 0x44d); mdelay(1); write_rtl8225(dev, 0x3, 0x441); mdelay(1); write_rtl8225(dev, 0x4, 0x8c3);mdelay(1); write_rtl8225(dev, 0x5, 0xc72);mdelay(1); // } write_rtl8225(dev, 0x6, 0xe6); mdelay(1); write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel])); mdelay(1); write_rtl8225(dev, 0x8, 0x3f); mdelay(1); write_rtl8225(dev, 0x9, 0x335); mdelay(1); write_rtl8225(dev, 0xa, 0x9d4); mdelay(1); write_rtl8225(dev, 0xb, 0x7bb); mdelay(1); write_rtl8225(dev, 0xc, 0x850); mdelay(1); write_rtl8225(dev, 0xd, 0xcdf); mdelay(1); write_rtl8225(dev, 0xe, 0x2b); mdelay(1); write_rtl8225(dev, 0xf, 0x114); mdelay(100); //if(priv->card_type != USB) /* maybe not needed even for 8185 */ // write_rtl8225(dev, 0x7, rtl8225_chan[channel]); write_rtl8225(dev, 0x0, 0x1b7); for(i=0;i<95;i++){ write_rtl8225(dev, 0x1, (u8)(i+1)); #if 0 if(priv->phy_ver == 1) /* version A */ write_rtl8225(dev, 0x2, rtl8225a_rxgain[i]); else #endif /* version B & C & D*/ write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]); } write_rtl8225(dev, 0x3, 0x80); write_rtl8225(dev, 0x5, 0x4); write_rtl8225(dev, 0x0, 0xb7); write_rtl8225(dev, 0x2, 0xc4d); if(priv->card_type == USB){ // force_pci_posting(dev); mdelay(200); write_rtl8225(dev, 0x2, 0x44d); // force_pci_posting(dev); mdelay(100); }//End of if(priv->card_type == USB) /* FIXME!! rtl8187 we have to check if calibrarion * is successful and eventually cal. again (repeat * the two write on reg 2) */ // Check for calibration status, 2005.11.17, data = read_rtl8225(dev, 6); if (!(data&0x00000080)) { write_rtl8225(dev, 0x02, 0x0c4d); force_pci_posting(dev); mdelay(200); write_rtl8225(dev, 0x02, 0x044d); force_pci_posting(dev); mdelay(100); data = read_rtl8225(dev, 6); if (!(data&0x00000080)) { DMESGW("RF Calibration Failed!!!!\n"); } } //force_pci_posting(dev); mdelay(200); //200 for 8187 // //if(priv->card_type != USB){ // write_rtl8225(dev, 0x2, 0x44d); // write_rtl8225(dev, 0x7, rtl8225_chan[channel]); // write_rtl8225(dev, 0x2, 0x47d); // // force_pci_posting(dev); // mdelay(100); // // write_rtl8225(dev, 0x2, 0x44d); // //} write_rtl8225(dev, 0x0, 0x2bf); if(priv->card_type != USB) rtl8185_rf_pins_enable(dev); //set up ZEBRA AGC table, 2005.11.17, for(i=0;i<128;i++){ data = rtl8225_agc[i]; addr = i + 0x80; //enable writing AGC table write_phy_ofdm(dev, 0xb, data); mdelay(1); write_phy_ofdm(dev, 0xa, addr); mdelay(1); } #if 0 for(i=0;i<128;i++){ write_phy_ofdm(dev, 0xb, rtl8225_agc[i]); mdelay(1); write_phy_ofdm(dev, 0xa, (u8)i+ 0x80); mdelay(1); } #endif force_pci_posting(dev); mdelay(1); write_phy_ofdm(dev, 0x0, 0x1); mdelay(1); write_phy_ofdm(dev, 0x1, 0x2); mdelay(1); write_phy_ofdm(dev, 0x2, ((priv->card_type == USB)? 0x42 : 0x62)); mdelay(1); write_phy_ofdm(dev, 0x3, 0x0); mdelay(1); write_phy_ofdm(dev, 0x4, 0x0); mdelay(1); write_phy_ofdm(dev, 0x5, 0x0); mdelay(1); write_phy_ofdm(dev, 0x6, 0x40); mdelay(1); write_phy_ofdm(dev, 0x7, 0x0); mdelay(1); write_phy_ofdm(dev, 0x8, 0x40); mdelay(1); write_phy_ofdm(dev, 0x9, 0xfe); mdelay(1); write_phy_ofdm(dev, 0xa, 0x8); mdelay(1); //write_phy_ofdm(dev, 0x18, 0xef); // } //} write_phy_ofdm(dev, 0xb, 0x80); mdelay(1); write_phy_ofdm(dev, 0xc, 0x1);mdelay(1); //if(priv->card_type != USB) write_phy_ofdm(dev, 0xd, 0x43); write_phy_ofdm(dev, 0xe, 0xd3);mdelay(1); #if 0 if(priv->card_8185 == 1){ if(priv->card_8185_Bversion) write_phy_ofdm(dev, 0xf, 0x20);/*ver B*/ else write_phy_ofdm(dev, 0xf, 0x28);/*ver C*/ }else{ #endif write_phy_ofdm(dev, 0xf, 0x38);mdelay(1); /*ver D & 8187*/ // } // if(priv->card_8185 == 1 && priv->card_8185_Bversion) // write_phy_ofdm(dev, 0x10, 0x04);/*ver B*/ // else write_phy_ofdm(dev, 0x10, 0x84);mdelay(1); /*ver C & D & 8187*/ write_phy_ofdm(dev, 0x11, 0x07);mdelay(1); /*agc resp time 700*/ // if(priv->card_8185 == 2){ /* Ver D & 8187*/ write_phy_ofdm(dev, 0x12, 0x20);mdelay(1); write_phy_ofdm(dev, 0x13, 0x20);mdelay(1); #if 0 }else{
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch) { struct r8180_priv *priv = ieee80211_priv(dev); // int GainIdx; // int GainSetting; int i; u8 power; u8 *cck_power_table; u8 max_cck_power_level; //u8 min_cck_power_level; u8 max_ofdm_power_level; u8 min_ofdm_power_level; u8 cck_power_level = 0xff & priv->chtxpwr[ch]; u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch]; max_cck_power_level = 15; //min_cck_power_level = 0; max_ofdm_power_level = 25; // 12 -> 25 min_ofdm_power_level = 10; /* CCK power setting */ if(cck_power_level > max_cck_power_level) cck_power_level = max_cck_power_level; cck_power_level += priv->cck_txpwr_base; if(cck_power_level > 35) cck_power_level = 35; if(ch == 14) cck_power_table = rtl8225z2_tx_power_cck_ch14; else cck_power_table = rtl8225z2_tx_power_cck; for(i=0;i<8;i++){ power = cck_power_table[i]; write_phy_cck(dev, 0x44 + i, power); } //write_nic_byte(dev, TX_GAIN_CCK, power); //2005.11.17, write_nic_byte(dev, TX_GAIN_CCK, ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]); force_pci_posting(dev); mdelay(1); /* OFDM power setting */ // Old: // if(ofdm_power_level > max_ofdm_power_level) // ofdm_power_level = 35; // ofdm_power_level += min_ofdm_power_level; // Latest: if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level)) ofdm_power_level = max_ofdm_power_level; else ofdm_power_level += min_ofdm_power_level; ofdm_power_level += priv->ofdm_txpwr_base; if(ofdm_power_level > 35) ofdm_power_level = 35; rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON); write_phy_ofdm(dev,2,0x42); write_phy_ofdm(dev,5,0); write_phy_ofdm(dev,6,0x40); write_phy_ofdm(dev,7,0); write_phy_ofdm(dev,8,0x40); //write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level); //2005.11.17, write_nic_byte(dev, TX_GAIN_OFDM, ZEBRA2_CCK_OFDM_GAIN_SETTING[ofdm_power_level]); force_pci_posting(dev); mdelay(1); //write_nic_byte(dev, TX_AGC_CONTROL,4); }
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch) { struct r8180_priv *priv = ieee80211_priv(dev); // int GainIdx; // int GainSetting; //int i; //u8 power; //u8 *cck_power_table; u8 max_cck_power_level; //u8 min_cck_power_level; u8 max_ofdm_power_level; u8 min_ofdm_power_level; // u8 cck_power_level = 0xff & priv->chtxpwr[ch];//-by amy 080312 // u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];//-by amy 080312 char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);//+by amy 080312 char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);//+by amy 080312 #if 0 // // CCX 2 S31, AP control of client transmit power: // 1. We shall not exceed Cell Power Limit as possible as we can. // 2. Tolerance is +/- 5dB. // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. // // TODO: // 1. 802.11h power contraint // // 071011, by rcnjko. // if( priv->OpMode == RT_OP_MODE_INFRASTRUCTURE && priv->bWithCcxCellPwr && ch == priv->dot11CurrentChannelNumber) { u8 CckCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr); u8 OfdmCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr); printk("CCX Cell Limit: %d dBm => CCK Tx power index : %d, OFDM Tx power index: %d\n", priv->CcxCellPwr, CckCellPwrIdx, OfdmCellPwrIdx); printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n", channel, CckTxPwrIdx, OfdmTxPwrIdx); if(cck_power_level > CckCellPwrIdx) cck_power_level = CckCellPwrIdx; if(ofdm_power_level > OfdmCellPwrIdx) ofdm_power_level = OfdmCellPwrIdx; printk("Altered CCK Tx power index : %d, OFDM Tx power index: %d\n", CckTxPwrIdx, OfdmTxPwrIdx); } #endif #ifdef ENABLE_DOT11D if(IS_DOT11D_ENABLE(priv->ieee80211) && IS_DOT11D_STATE_DONE(priv->ieee80211) ) { //PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(priv->ieee80211); u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch); u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm); u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm); //printk("Max Tx Power dBm (%d) => CCK Tx power index : %d, OFDM Tx power index: %d\n", MaxTxPwrInDbm, CckMaxPwrIdx, OfdmMaxPwrIdx); //printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n", // ch, cck_power_level, ofdm_power_level); if(cck_power_level > CckMaxPwrIdx) cck_power_level = CckMaxPwrIdx; if(ofdm_power_level > OfdmMaxPwrIdx) ofdm_power_level = OfdmMaxPwrIdx; } //priv->CurrentCckTxPwrIdx = cck_power_level; //priv->CurrentOfdmTxPwrIdx = ofdm_power_level; #endif max_cck_power_level = 15; max_ofdm_power_level = 25; // 12 -> 25 min_ofdm_power_level = 10; #ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL818X_S if(cck_power_level > 35) { cck_power_level = 35; } // // Set up CCK TXAGC. suggested by SD3 SY. // write_nic_byte(dev, CCK_TXAGC, (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]) ); //printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level])); force_pci_posting(dev); mdelay(1); #else /* CCK power setting */ if(cck_power_level > max_cck_power_level) cck_power_level = max_cck_power_level; cck_power_level += priv->cck_txpwr_base; if(cck_power_level > 35) cck_power_level = 35; if(ch == 14) cck_power_table = rtl8225z2_tx_power_cck_ch14; else cck_power_table = rtl8225z2_tx_power_cck; for(i=0;i<8;i++){ power = cck_power_table[i]; write_phy_cck(dev, 0x44 + i, power); } //write_nic_byte(dev, TX_GAIN_CCK, power); //2005.11.17, write_nic_byte(dev, CCK_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]); force_pci_posting(dev); mdelay(1); #endif #endif /* OFDM power setting */ // Old: // if(ofdm_power_level > max_ofdm_power_level) // ofdm_power_level = 35; // ofdm_power_level += min_ofdm_power_level; // Latest: /* if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level)) ofdm_power_level = max_ofdm_power_level; else ofdm_power_level += min_ofdm_power_level; ofdm_power_level += priv->ofdm_txpwr_base; */ if(ofdm_power_level > 35) ofdm_power_level = 35; // rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON); //rtl8185_set_anaparam2(dev, ANAPARM2_ASIC_ON); if (priv->up == 0) { //must add these for rtl8185B down, xiong-2006-11-21 write_phy_ofdm(dev,2,0x42); write_phy_ofdm(dev,5,0); write_phy_ofdm(dev,6,0x40); write_phy_ofdm(dev,7,0); write_phy_ofdm(dev,8,0x40); } //write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level); //2005.11.17, #ifdef CONFIG_RTL818X_S write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]); #else write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]*2); #endif if(ofdm_power_level<=11) { // write_nic_dword(dev,PHY_ADR,0x00005c87); // write_nic_dword(dev,PHY_ADR,0x00005c89); write_phy_ofdm(dev,0x07,0x5c); write_phy_ofdm(dev,0x09,0x5c); } if(ofdm_power_level<=17) { // write_nic_dword(dev,PHY_ADR,0x00005487); // write_nic_dword(dev,PHY_ADR,0x00005489); write_phy_ofdm(dev,0x07,0x54); write_phy_ofdm(dev,0x09,0x54); } else { // write_nic_dword(dev,PHY_ADR,0x00005087); // write_nic_dword(dev,PHY_ADR,0x00005089); write_phy_ofdm(dev,0x07,0x50); write_phy_ofdm(dev,0x09,0x50); } force_pci_posting(dev); mdelay(1); }