static u_char
spic_call1(struct spic_softc *sc, u_char dev) {
busy_wait(sc);
write_port2(sc, dev);
read_port2(sc);
return read_port1(sc);
}
/* check OCI or TOI */
void m6800_cpu_device::check_timer_event()
{
/* OCI */
if( CTD >= OCD)
{
OCH++; // next IRQ point
m_tcsr |= TCSR_OCF;
m_pending_tcsr |= TCSR_OCF;
MODIFIED_tcsr;
if((m_tcsr & TCSR_EOCI) && m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
if ( !(CC & 0x10) && (m_tcsr & TCSR_EOCI))
TAKE_OCI;
// if output on P21 is enabled, let's do it
if (m_port2_ddr & 2)
{
m_port2_data &= ~2;
m_port2_data |= (m_tcsr & TCSR_OLVL) << 1;
m_port2_written = 1;
write_port2();
}
}
/* TOI */
if( CTD >= TOD)
{
TOH++; // next IRQ point
#if 0
CLEANUP_COUNTERS();
#endif
m_tcsr |= TCSR_TOF;
m_pending_tcsr |= TCSR_TOF;
MODIFIED_tcsr;
if((m_tcsr & TCSR_ETOI) && m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
if ( !(CC & 0x10) && (m_tcsr & TCSR_ETOI))
TAKE_TOI;
}
/* set next event */
SET_TIMER_EVENT;
}
void m6800_cpu_device::serial_transmit()
{
//logerror("M6800 '%s' Tx Tick\n", tag());
if (m_trcsr & M6800_TRCSR_TE)
{
// force Port 2 bit 4 as output
m_port2_ddr |= M6800_PORT2_IO4;
switch (m_txstate)
{
case M6800_TX_STATE_INIT:
m_tx = 1;
m_txbits++;
if (m_txbits == 10)
{
m_txstate = M6800_TX_STATE_READY;
m_txbits = M6800_SERIAL_START;
}
break;
case M6800_TX_STATE_READY:
switch (m_txbits)
{
case M6800_SERIAL_START:
if (m_trcsr & M6800_TRCSR_TDRE)
{
// transmit buffer is empty, send nothing
return;
}
else
{
// transmit buffer is full, send data
// load TDR to shift register
m_tsr = m_tdr;
// transmit buffer is empty, set TDRE flag
m_trcsr |= M6800_TRCSR_TDRE;
// send start bit '0'
m_tx = 0;
m_txbits++;
//logerror("M6800 '%s' Transmit START Data %02x\n", tag(), m_tsr);
}
break;
case M6800_SERIAL_STOP:
// send stop bit '1'
m_tx = 1;
CHECK_IRQ_LINES();
m_txbits = M6800_SERIAL_START;
//logerror("M6800 '%s' Transmit STOP\n", tag());
break;
default:
// send data bit '0' or '1'
m_tx = m_tsr & 0x01;
// shift transmit register
m_tsr >>= 1;
//logerror("M6800 '%s' Transmit Bit %u: %u\n", tag(), m_txbits, m_tx);
m_txbits++;
break;
}
break;
}
m_out_sertx_func((m_tx == 1) ? ASSERT_LINE : CLEAR_LINE);
m_port2_written = 1;
write_port2();
}
