static void ide_itdm320_outsw (unsigned long port, void *addr, u32 count)
{
volatile u16 *d_ptr;
unsigned long dest_addr;
if ( count <= SECTOR_WORDS ) {
writesw(port, addr, count);
return;
}
d_ptr = (volatile u16*) addr;
dest_addr = virt_to_phys((void*) d_ptr);
if (((u32) dest_addr) & 0x2) {
writesw(port, addr, 1);
dest_addr += 2;
count -= 2;
if (!count) return;
}//if
if ( 0 != (count&15) ) {
printk( "Warning: word count=%d\n", count );
}
// flush write data to DRAM
// arm926_dma_flush_range((unsigned long)addr, (unsigned long)addr + count );
consistent_sync( addr, count, DMA_TO_DEVICE );
while (inw(IO_EMIF_DMACTL) & 0x0001); // wait for DMA completion
outw(0x0830, IO_SDRAM_SDDMASEL); // MTC 1 burst DMA
outw(0x0003, IO_EMIF_DMAMTCSEL); // DMA MTC Select: CS3
outw(((port & 0x0FFF0000) >> 16) |
(1 << 15), IO_EMIF_MTCADDH);
outw(port & 0x0000FFFF, IO_EMIF_MTCADDL);
outw((dest_addr & 0x7FFF0000) >> 16, IO_EMIF_AHBADDH);
outw(dest_addr & 0x0000FFFF, IO_EMIF_AHBADDL);
SET_DMA_SIZE( count );
/* Start the DMA transfer */
outw(0x0000, IO_EMIF_DMACTL);
outw(inw(IO_EMIF_DMACTL) | 1, IO_EMIF_DMACTL);
}
static void at91_ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
void *buf, unsigned int len)
{
ide_hwif_t *hwif = drive->hwif;
struct ide_io_ports *io_ports = &hwif->io_ports;
u8 chipselect = hwif->select_data;
unsigned long mode;
pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
enter_16bit(chipselect, mode);
writesw((void __iomem *)io_ports->data_addr, buf, len / 2);
leave_16bit(chipselect, mode);
}
static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
u16 *buf, int count)
{
writesw(host->ctl + (addr << host->bus_shift), buf, count);
}
static void ide_itdm320_outsw (unsigned long port, void *addr, u32 count)
{
writesw(port, addr, count);
}
