/* AMD K7 machine check */ int amd_k7_mcheck_init(struct cpuinfo_x86 *c) { u32 l, h; int i; /* Check for PPro style MCA; our caller has confirmed MCE support. */ if (!cpu_has(c, X86_FEATURE_MCA)) return 0; x86_mce_vector_register(k7_machine_check); rdmsr (MSR_IA32_MCG_CAP, l, h); if (l & (1<<8)) /* Control register present ? */ wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); nr_mce_banks = l & 0xff; /* Clear status for MC index 0 separately, we don't touch CTL, * as some Athlons cause spurious MCEs when its enabled. */ wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0); for (i=1; i<nr_mce_banks; i++) { wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); } set_in_cr4 (X86_CR4_MCE); printk (KERN_INFO "CPU%d: AMD K7 machine check reporting enabled.\n", smp_processor_id()); return 1; }
enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *ci) { uint32_t i; enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(ci); /* Assume that machine check support is available. * The minimum provided support is at least the K8. */ mce_handler_init(); x86_mce_vector_register(mcheck_cmn_handler); mce_need_clearbank_register(amd_need_clearbank_scan); for ( i = 0; i < nr_mce_banks; i++ ) { if ( quirkflag == MCEQUIRK_K8_GART && i == 4 ) mcequirk_amd_apply(quirkflag); else { /* Enable error reporting of all errors */ wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL); wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL); } } if ( ci->x86 == 0xf ) return mcheck_amd_k8; if ( quirkflag == MCEQUIRK_F10_GART ) mcequirk_amd_apply(quirkflag); x86_mce_callback_register(amd_f10_handler); mce_recoverable_register(mc_amd_recoverable_scan); mce_register_addrcheck(mc_amd_addrcheck); return mcheck_amd_famXX; }