// Initialize hardware (including startup) void netxeth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) { PNETX_ETH_PORT_INFO ptPortInfo = sc->driver_private; cyg_uint32 uiPhyData; cyg_uint32 ulPort = ptPortInfo->ulPort; cyg_uint32 ulIdx; cyg_uint32 ulFifoOffset = 8 * ulPort; cyg_uint16* pusMAC = (cyg_uint16*)ptPortInfo->abMAC; xc_reset(ptPortInfo->ulPort); xc_load(ptPortInfo->ulPort, ptPortInfo->pulRPECFirmware, NULL, ptPortInfo->pulxMACRPUFirmware, ptPortInfo->pulxMACTPUFirmware); // local mac config ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_TRAFFIC_CLASS_ARRANGEMENT / sizeof(cyg_uint32)] = (0x8 << SRT_ETHMAC_TRAFFIC_CLASS_ARRANGEMENT_VAL); for(ulIdx = 1; ulIdx < (MAX_SEND_SLOTS + 1); ulIdx++) { ptPortInfo->atSendFrames[ulIdx - 1].ulSegment = ptPortInfo->ulPort; ptPortInfo->atSendFrames[ulIdx - 1].ulFrameNr = ulIdx; ptPortInfo->atSendFrames[ulIdx - 1].ulKey = 0; ptPortInfo->atSendFrames[ulIdx - 1].fUsed = false; } for(ulIdx = MAX_SEND_SLOTS + 1; ulIdx < MAX_SLOTS; ulIdx++) { FIFO_POINTER tPtr = {0}; tPtr.tBf.uiSegment = ptPortInfo->ulPort; tPtr.tBf.uiFrameNr = ulIdx; s_ptFifoArea->aulPfifo[ulFifoOffset + EMPTY_PTR_FIFO] = tPtr.uiVal; } /* Enable all interrupt sources */ ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_IND_HI / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_IND_HI_VAL; ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_IND_LO / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_IND_LO_VAL; ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_CON_HI / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_CON_HI_VAL; ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_INTERRUPTS_ENABLE_CON_LO / sizeof(cyg_uint32)] = MSK_ETHMAC_INTERRUPTS_ENABLE_CON_LO_VAL; ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_LOCAL_MAC_ADDRESS_HI / sizeof(cyg_uint32)] = pusMAC[2]; ptPortInfo->pulRPECDram[REL_Adr_ETHMAC_LOCAL_MAC_ADDRESS_LO / sizeof(cyg_uint32)] = (pusMAC[1] << 16) | pusMAC[0]; xc_start(ptPortInfo->ulPort); //Wakeup phy from powerdown PhyMDIO(s_abPhyAddresses[ptPortInfo->ulPort], MDIO_READ, DRV_CB12_CONTROL, &uiPhyData); uiPhyData = DRV_CB12_CONTROL_AUTO_NEG_ENABLE; PhyMDIO(s_abPhyAddresses[ptPortInfo->ulPort], MDIO_WRITE, DRV_CB12_CONTROL, &uiPhyData); cyg_drv_interrupt_unmask(ptPortInfo->ulInterrupt); }
static void netx_eth_timeout(struct net_device *ndev) { struct netx_eth_priv *priv = netdev_priv(ndev); int i; printk(KERN_ERR "%s: transmit timed out, resetting\n", ndev->name); spin_lock_irq(&priv->lock); xc_reset(priv->xc); xc_start(priv->xc); for (i=2; i<=18; i++) pfifo_push(EMPTY_PTR_FIFO(priv->id), FIFO_PTR_FRAMENO(i) | FIFO_PTR_SEGMENT(priv->id)); spin_unlock_irq(&priv->lock); netif_wake_queue(ndev); }