int board_eth_init(bd_t *bis) { u32 ret = 0; #ifdef CONFIG_XILINX_AXIEMAC ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, XILINX_AXIDMA_BASEADDR); #endif #ifdef CONFIG_XILINX_EMACLITE u32 txpp = 0; u32 rxpp = 0; # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG txpp = 1; # endif # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG rxpp = 1; # endif ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, txpp, rxpp); #endif #if defined(CONFIG_ZYNQ_GEM) # if defined(CONFIG_ZYNQ_GEM0) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); # endif # if defined(CONFIG_ZYNQ_GEM1) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); # endif #endif return ret; }
int board_eth_init(bd_t *bis) { int ret = 0; #ifdef CONFIG_XILINX_AXIEMAC ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, XILINX_AXIDMA_BASEADDR); #endif #ifdef CONFIG_XILINX_EMACLITE u32 txpp = 0; u32 rxpp = 0; # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG txpp = 1; # endif # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG rxpp = 1; # endif ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, txpp, rxpp); #endif #ifdef CONFIG_XILINX_LL_TEMAC # ifdef XILINX_LLTEMAC_BASEADDR # ifdef XILINX_LLTEMAC_FIFO_BASEADDR ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR); # elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR # if XILINX_LLTEMAC_SDMA_USE_DCR == 1 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, XILINX_LL_TEMAC_M_SDMA_DCR, XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); # else ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, XILINX_LL_TEMAC_M_SDMA_PLB, XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); # endif # endif # endif # ifdef XILINX_LLTEMAC_BASEADDR1 # ifdef XILINX_LLTEMAC_FIFO_BASEADDR1 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1); # elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 # if XILINX_LLTEMAC_SDMA_USE_DCR == 1 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, XILINX_LL_TEMAC_M_SDMA_DCR, XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); # else ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, XILINX_LL_TEMAC_M_SDMA_PLB, XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); # endif # endif # endif #endif return ret; }
int board_eth_init(bd_t *bis) { int ret = 0; #ifdef CONFIG_XILINX_AXIEMAC ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR); #endif #ifdef CONFIG_XILINX_EMACLITE ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR); #endif #ifdef CONFIG_XILINX_LL_TEMAC ret |= xilinx_ll_temac_initialize(bis, XILINX_LLTEMAC_BASEADDR); #endif return ret; }
int board_eth_init(bd_t *bis) { u32 ret = 0; u_int8_t mac[6]; if (zx3_read_mac_address (mac, 0)) { int err; /* set address env if not already set */ err = eth_setenv_enetaddr("ethaddr", mac); if (err) printf("Failed to set MAC address 0 from EEPROM to env.\n"); } #ifdef CONFIG_XILINX_AXIEMAC ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, XILINX_AXIDMA_BASEADDR); #endif #ifdef CONFIG_XILINX_EMACLITE u32 txpp = 0; u32 rxpp = 0; # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG txpp = 1; # endif # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG rxpp = 1; # endif ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, txpp, rxpp); #endif #if defined(CONFIG_ZYNQ_GEM) # if defined(CONFIG_ZYNQ_GEM0) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); # endif # if defined(CONFIG_ZYNQ_GEM1) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); # endif #endif return ret; }