示例#1
0
文件: yucca.c 项目: 274914765/C
static void __init
yucca_setup_hoses(void)
{
    struct pci_controller *hose;
    char name[20];
    int i;

    if (0 && ppc440spe_init_pcie()) {
        printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
        return;
    }

    for (i = 0; i <= 2; ++i) {
        if (!yucca_pcie_card_present(i))
            continue;

        printk(KERN_INFO "PCIE%d: card present\n", i);
        yucca_setup_pcie_fpga_rootpoint(i);
        if (ppc440spe_init_pcie_rootport(i)) {
            printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
            continue;
        }

        hose = pcibios_alloc_controller();
        if (!hose)
            return;

        sprintf(name, "PCIE%d host bridge", i);
        pci_init_resource(&hose->io_resource,
                  YUCCA_PCIX_LOWER_IO,
                  YUCCA_PCIX_UPPER_IO,
                  IORESOURCE_IO,
                  name);

        hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
            i * YUCCA_PCIE_MEM_SIZE;
        hose->mem_space.end   = hose->mem_space.start +
            YUCCA_PCIE_MEM_SIZE - 1;

        pci_init_resource(&hose->mem_resources[0],
                  hose->mem_space.start,
                  hose->mem_space.end,
                  IORESOURCE_MEM,
                  name);

        hose->first_busno = 0;
        hose->last_busno  = 15;
        hose_type[hose->index] = HOSE_PCIE0 + i;

        ppc440spe_setup_pcie(hose, i);
        hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
    }

    ppc_md.pci_swizzle = common_swizzle;
    ppc_md.pci_map_irq = yucca_map_irq;
}
void pcie_setup_hoses(int busno)
{
	struct pci_controller *hose;
	int i, bus;
	char *env;
	unsigned int delay;

	/*
	 * assume we're called after the PCIX hose is initialized, which takes
	 * bus ID 0 and therefore start numbering PCIe's from 1.
	 */
	bus = busno;
	for (i = 0; i <= 2; i++) {
		/* Check for yucca card presence */
		if (!yucca_pcie_card_present(i))
			continue;

#ifdef PCIE_ENDPOINT
 		yucca_setup_pcie_fpga_endpoint(i);
 		if (ppc440spe_init_pcie_endport(i)) {
#else
		yucca_setup_pcie_fpga_rootpoint(i);
		if (ppc440spe_init_pcie_rootport(i)) {
#endif
			printf("PCIE%d: initialization failed\n", i);
			continue;
		}

		hose = &pcie_hose[i];
		hose->first_busno = bus;
		hose->last_busno = bus;
		hose->current_busno = bus;

		/* setup mem resource */
		pci_set_region(hose->regions + 0,
			CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			CFG_PCIE_MEMSIZE,
			PCI_REGION_MEM
			);
		hose->region_count = 1;
		pci_register_hose(hose);

#ifdef PCIE_ENDPOINT
		ppc440spe_setup_pcie_endpoint(hose, i);
		/*
		 * Reson for no scanning is endpoint can not generate
		 * upstream configuration accesses.
		 */
#else
		ppc440spe_setup_pcie_rootpoint(hose, i);

		env = getenv ("pciscandelay");
		if (env != NULL) {
			delay = simple_strtoul (env, NULL, 10);
			if (delay > 5)
				printf ("Warning, expect noticable delay before PCIe"
					"scan due to 'pciscandelay' value!\n");
			mdelay (delay * 1000);
		}

		/*
		 * Config access can only go down stream
		 */
		hose->last_busno = pci_hose_scan(hose);
		bus = hose->last_busno + 1;
#endif
	}
}
#endif	/* defined(CONFIG_PCI) */

int misc_init_f (void)
{
	uint reg;
#if defined(CONFIG_STRESS)
	uint i ;
	uint disp;
#endif

	out16(FPGA_REG10, (in16(FPGA_REG10) &
			~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
				FPGA_REG10_10MHZ_ENABLE |
				FPGA_REG10_100MHZ_ENABLE |
				FPGA_REG10_GIGABIT_ENABLE |
				FPGA_REG10_FULL_DUPLEX );

	udelay(10000);	/* wait 10ms */

	out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));

	/* minimal init for PCIe */
	/* pci express 0 Endpoint Mode */
	mfsdr(SDR0_PE0DLPSET, reg);
	reg &= (~0x00400000);
	mtsdr(SDR0_PE0DLPSET, reg);
	/* pci express 1 Rootpoint  Mode */
	mfsdr(SDR0_PE1DLPSET, reg);
	reg |= 0x00400000;
	mtsdr(SDR0_PE1DLPSET, reg);
	/* pci express 2 Rootpoint  Mode */
	mfsdr(SDR0_PE2DLPSET, reg);
	reg |= 0x00400000;
	mtsdr(SDR0_PE2DLPSET, reg);

	out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
				~FPGA_REG1C_PE0_ROOTPOINT &
				~FPGA_REG1C_PE1_ENDPOINT  &
				~FPGA_REG1C_PE2_ENDPOINT));

#if defined(CONFIG_STRESS)
	/*
	 * all this setting done by linux only needed by stress an charac. test
	 * procedure
	 * PCIe 1 Rootpoint PCIe2 Endpoint
	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
	 * Power Level
	 */
	for (i = 0, disp = 0; i < 8; i++, disp += 3) {
		mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
	}

	/*
	 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
	 * Power Level
	 */
	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
		mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
	}

	/*
	 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
	 * Power Level
	 */
	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
		mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
	}

	reg = 0x21242222;
	mtsdr(SDR0_PE2UTLSET1, reg);
	reg = 0x11000000;
	mtsdr(SDR0_PE2UTLSET2, reg);
	/* pci express 1 Endpoint  Mode */
	reg = 0x00004000;
	mtsdr(SDR0_PE2DLPSET, reg);

	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
#endif
	return 0;
}