static int zd1211b_al2230_finalize_rf(struct zd_chip *chip) { int r; static const struct zd_ioreq16 ioreqs[] = { { CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 }, { CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 }, { CR203, 0x06 }, { }, { CR240, 0x80 }, }; r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); if (r) return r; /* related to antenna selection? */ if (chip->new_phy_layout) { r = zd_iowrite16_locked(chip, 0xe1, CR9); if (r) return r; } return zd_iowrite16_locked(chip, 0x06, CR203); }
static int zd1211b_al7230b_set_channel(struct zd_rf *rf, u8 channel) { int r; const u32 *rv = chan_rv[channel-1]; struct zd_chip *chip = zd_rf_to_chip(rf); r = zd_iowrite16_locked(chip, 0x57, CR240); if (r) return r; r = zd_iowrite16_locked(chip, 0xe4, CR9); if (r) return r; /* PLL_OFF */ r = zd_iowrite16_locked(chip, 0x2f, CR251); if (r) return r; r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv)); if (r) return r; r = zd_rfwrite_cr_locked(chip, 0x3c9000); if (r) return r; r = zd_rfwrite_cr_locked(chip, 0xf15d58); if (r) return r; r = zd_iowrite16a_locked(chip, ioreqs_sw, ARRAY_SIZE(ioreqs_sw)); if (r) return r; r = zd_rfwritev_cr_locked(chip, rv, 2); if (r) return r; r = zd_rfwrite_cr_locked(chip, 0x3c9000); if (r) return r; r = zd_iowrite16_locked(chip, 0x7f, CR251); if (r) return r; return zd1211b_al7230b_finalize(chip); }
static int zd1211_al7230b_set_channel(struct zd_rf *rf, u8 channel) { int r; const u32 *rv = chan_rv[channel-1]; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs[] = { /* PLL_ON */ { CR251, 0x3f }, { CR203, 0x06 }, { CR240, 0x08 }, }; r = zd_iowrite16_locked(chip, 0x57, CR240); if (r) return r; /* PLL_OFF */ r = zd_iowrite16_locked(chip, 0x2f, CR251); if (r) return r; r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv)); if (r) return r; r = zd_rfwrite_cr_locked(chip, 0x3c9000); if (r) return r; r = zd_rfwrite_cr_locked(chip, 0xf15d58); if (r) return r; r = zd_iowrite16a_locked(chip, ioreqs_sw, ARRAY_SIZE(ioreqs_sw)); if (r) return r; r = zd_rfwritev_cr_locked(chip, rv, 2); if (r) return r; r = zd_rfwrite_cr_locked(chip, 0x3c9000); if (r) return r; return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); }
int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) { int r; mutex_lock(&chip->mutex); r = zd_iowrite16_locked(chip, value, addr); mutex_unlock(&chip->mutex); return r; }
static int uw2453_set_channel(struct zd_rf *rf, u8 channel) { int r; u16 vco_cfg; int config = UW2453_PRIV(rf)->config; bool autocal = (config == -1); struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs[] = { { CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 }, { CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 }, }; r = uw2453_synth_set_channel(chip, channel, autocal); if (r) return r; if (autocal) vco_cfg = UW2453_AUTOCAL_VCO_CFG; else vco_cfg = uw2453_std_vco_cfg[config][CHAN_TO_PAIRIDX(channel)]; r = uw2453_write_vco_cfg(chip, vco_cfg); if (r) return r; r = uw2453_init_mode(chip); if (r) return r; r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); if (r) return r; r = uw2453_set_tx_gain_level(chip, channel); if (r) return r; return zd_iowrite16_locked(chip, 0x06, CR203); }
static int uw2453_init_hw(struct zd_rf *rf) { int i, r; int found_config = -1; u16 intr_status; struct zd_chip *chip = zd_rf_to_chip(rf); static const struct zd_ioreq16 ioreqs[] = { { CR10, 0x89 }, { CR15, 0x20 }, { CR17, 0x28 }, /* 6112 no change */ { CR23, 0x38 }, { CR24, 0x20 }, { CR26, 0x93 }, { CR27, 0x15 }, { CR28, 0x3e }, { CR29, 0x00 }, { CR33, 0x28 }, { CR34, 0x30 }, { CR35, 0x43 }, /* 6112 3e->43 */ { CR41, 0x24 }, { CR44, 0x32 }, { CR46, 0x92 }, /* 6112 96->92 */ { CR47, 0x1e }, { CR48, 0x04 }, /* 5602 Roger */ { CR49, 0xfa }, { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 }, { CR91, 0x00 }, { CR92, 0x0a }, { CR98, 0x8d }, { CR99, 0x28 }, { CR100, 0x02 }, { CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */ { CR102, 0x27 }, { CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f 6221 1f->1c */ { CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */ { CR109, 0x13 }, { CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */ { CR111, 0x13 }, { CR112, 0x1f }, { CR113, 0x27 }, { CR114, 0x23 }, /* 6221 27->23 */ { CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */ { CR116, 0x24 }, /* 6220 1c->24 */ { CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */ { CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */ { CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */ { CR120, 0x4f }, { CR121, 0x1f }, /* 6220 4f->1f */ { CR122, 0xf0 }, { CR123, 0x57 }, { CR125, 0xad }, { CR126, 0x6c }, { CR127, 0x03 }, { CR128, 0x14 }, /* 6302 12->11 */ { CR129, 0x12 }, /* 6301 10->0f */ { CR130, 0x10 }, { CR137, 0x50 }, { CR138, 0xa8 }, { CR144, 0xac }, { CR146, 0x20 }, { CR252, 0xff }, { CR253, 0xff }, }; static const u32 rv[] = { UW2453_REGWRITE(4, 0x2b), /* configure reciever gain */ UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */ UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */ UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */ /* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins, * RSSI circuit powered down, reduced RSSI range */ UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */ /* synthesizer configuration for channel 1 */ UW2453_REGWRITE(1, 0x47), UW2453_REGWRITE(2, 0x999), /* disable manual VCO band selection */ UW2453_REGWRITE(3, 0x7602), /* enable manual VCO band selection, configure current level */ UW2453_REGWRITE(3, 0x46063), }; r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); if (r) return r; r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS); if (r) return r; r = uw2453_init_mode(chip); if (r) return r; /* Try all standard VCO configuration settings on channel 1 */ for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) { /* Configure synthesizer for channel 1 */ r = uw2453_synth_set_channel(chip, 1, false); if (r) return r; /* Write VCO config */ r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]); if (r) return r; /* ack interrupt event */ r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG); if (r) return r; /* check interrupt status */ r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG); if (r) return r; if (!(intr_status & 0xf)) { dev_dbg_f(zd_chip_dev(chip), "PLL locked on configuration %d\n", i); found_config = i; break; } } if (found_config == -1) { /* autocal */ dev_dbg_f(zd_chip_dev(chip), "PLL did not lock, using autocal\n"); r = uw2453_synth_set_channel(chip, 1, true); if (r) return r; r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG); if (r) return r; } /* To match the vendor driver behaviour, we use the configuration after * the one that produced a lock. */ UW2453_PRIV(rf)->config = found_config + 1; return zd_iowrite16_locked(chip, 0x06, CR203); }
static int zd1211_al7230b_init_hw(struct zd_rf *rf) { int r; struct zd_chip *chip = zd_rf_to_chip(rf); /* All of these writes are identical to AL2230 unless otherwise * specified */ static const struct zd_ioreq16 ioreqs_1[] = { /* This one is 7230-specific, and happens before the rest */ { CR240, 0x57 }, { }, { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 }, { CR44, 0x33 }, /* This value is different for 7230 (was: 0x2a) */ { CR106, 0x22 }, { CR107, 0x1a }, { CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b }, { CR112, 0x2b }, { CR119, 0x0a }, /* This happened further down in AL2230, * and the value changed (was: 0xe0) */ { CR122, 0xfc }, { CR10, 0x89 }, /* for newest (3rd cut) AL2300 */ { CR17, 0x28 }, { CR26, 0x93 }, { CR34, 0x30 }, /* for newest (3rd cut) AL2300 */ { CR35, 0x3e }, { CR41, 0x24 }, { CR44, 0x32 }, /* for newest (3rd cut) AL2300 */ { CR46, 0x96 }, { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 }, { CR92, 0x0a }, { CR99, 0x28 }, /* This value is different for 7230 (was: 0x00) */ { CR100, 0x02 }, { CR101, 0x13 }, { CR102, 0x27 }, /* This value is different for 7230 (was: 0x24) */ { CR106, 0x22 }, /* This value is different for 7230 (was: 0x2a) */ { CR107, 0x3f }, { CR109, 0x09 }, /* This value is different for 7230 (was: 0x13) */ { CR110, 0x1f }, { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 }, { CR114, 0x27 }, /* for newest (3rd cut) AL2300 */ { CR115, 0x24 }, /* This value is different for 7230 (was: 0x24) */ { CR116, 0x3f }, /* This value is different for 7230 (was: 0xf4) */ { CR117, 0xfa }, { CR118, 0xfc }, { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 }, { CR137, 0x88 }, /* This one is 7230-specific */ { CR138, 0xa8 }, /* This value is different for 7230 (was: 0xff) */ { CR252, 0x34 }, /* This value is different for 7230 (was: 0xff) */ { CR253, 0x34 }, /* PLL_OFF */ { CR251, 0x2f }, }; static const struct zd_ioreq16 ioreqs_2[] = { { CR251, 0x3f }, /* PLL_ON */ { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, { CR38, 0x38 }, { CR136, 0xdf }, }; r = zd_iowrite16a_locked(chip, ioreqs_1, ARRAY_SIZE(ioreqs_1)); if (r) return r; r = zd_rfwritev_cr_locked(chip, chan_rv[0], ARRAY_SIZE(chan_rv[0])); if (r) return r; r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv)); if (r) return r; r = zd_rfwritev_cr_locked(chip, rv_init1, ARRAY_SIZE(rv_init1)); if (r) return r; r = zd_iowrite16a_locked(chip, ioreqs_2, ARRAY_SIZE(ioreqs_2)); if (r) return r; r = zd_rfwritev_cr_locked(chip, rv_init2, ARRAY_SIZE(rv_init2)); if (r) return r; r = zd_iowrite16_locked(chip, 0x06, CR203); if (r) return r; r = zd_iowrite16_locked(chip, 0x80, CR240); if (r) return r; return 0; }