static void __init zeus_init(void)
{
u16 dm9000_msc = 0xe279;
system_rev = __raw_readw(ZEUS_CPLD_VERSION);
pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
/* Fix timings for dm9000s (CS1/CS2)*/
MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
pm_power_off = zeus_power_off;
pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
pxa_set_ohci_info(&zeus_ohci_platform_data);
if (zeus_setup_fb_gpios())
pr_err("Failed to setup fb gpios\n");
else
set_pxa_fb_info(&zeus_fb_info);
pxa_set_mci_info(&zeus_mci_platform_data);
pxa_set_udc_info(&zeus_udc_info);
pxa_set_ac97_info(&zeus_ac97_info);
pxa_set_i2c_info(NULL);
i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
}
static void __init zeus_init(void)
{
u16 dm9000_msc = DM9K_MSC_VALUE;
u32 msc0, msc1;
system_rev = __raw_readw(ZEUS_CPLD_VERSION);
pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
/* Fix timings for dm9000s (CS1/CS2)*/
msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
__raw_writel(msc0, MSC0);
__raw_writel(msc1, MSC1);
pm_power_off = zeus_power_off;
zeus_setup_apm();
pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
zeus_register_ohci();
if (zeus_setup_fb_gpios())
pr_err("Failed to setup fb gpios\n");
else
pxa_set_fb_info(NULL, &zeus_fb_info);
pxa_set_mci_info(&zeus_mci_platform_data);
pxa_set_udc_info(&zeus_udc_info);
pxa_set_ac97_info(&zeus_ac97_info);
pxa_set_i2c_info(NULL);
i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
regulator_has_full_constraints();
}
