/** * zynqmp_pll_enable - Enable clock * @hw: Handle between common and hardware-specific interfaces * * Return: 0 always */ static int zynqmp_pll_enable(struct clk_hw *hw) { u32 reg; struct zynqmp_pll *clk = to_zynqmp_pll(hw); if (zynqmp_pll_is_enabled(hw)) return 0; pr_info("PLL: enable\n"); reg = zynqmp_pm_mmio_readl(clk->pll_ctrl); reg |= PLLCTRL_BP_MASK; zynqmp_pm_mmio_writel(reg, clk->pll_ctrl); reg |= PLLCTRL_RESET_MASK; zynqmp_pm_mmio_writel(reg, clk->pll_ctrl); reg &= ~(PLLCTRL_RESET_MASK); zynqmp_pm_mmio_writel(reg, clk->pll_ctrl); while (!(zynqmp_pm_mmio_readl(clk->pll_status) & (1 << clk->lockbit))) cpu_relax(); reg &= ~PLLCTRL_BP_MASK; zynqmp_pm_mmio_writel(reg, clk->pll_ctrl); return 0; }
/** * zynqmp_pll_disable - Disable clock * @hw: Handle between common and hardware-specific interfaces * */ static void zynqmp_pll_disable(struct clk_hw *hw) { struct zynqmp_pll *clk = to_zynqmp_pll(hw); if (!zynqmp_pll_is_enabled(hw)) return; pr_info("PLL: shutdown\n"); /* shut down PLL */ zynqmp_pm_mmio_write((u32)(ulong)clk->pll_ctrl, PLLCTRL_RESET_MASK, PLLCTRL_RESET_VAL); }