void BOARD::DrawHighLight( EDA_DRAW_PANEL* am_canvas, wxDC* DC, int aNetCode )
{
GR_DRAWMODE draw_mode;
if( IsHighLightNetON() )
draw_mode = GR_HIGHLIGHT | GR_OR;
else
draw_mode = GR_AND | GR_HIGHLIGHT;
// Redraw ZONE_CONTAINERS
BOARD::ZONE_CONTAINERS& zones = m_ZoneDescriptorList;
for( BOARD::ZONE_CONTAINERS::iterator zc = zones.begin(); zc!=zones.end(); ++zc )
{
if( (*zc)->GetNet() == aNetCode )
{
(*zc)->Draw( am_canvas, DC, draw_mode );
}
}
// Redraw any pads that have aNetCode
for( MODULE* module = m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
{
if( pad->GetNet() == aNetCode )
{
pad->Draw( am_canvas, DC, draw_mode );
}
}
}
// Redraw track and vias that have aNetCode
for( TRACK* seg = m_Track; seg; seg = seg->Next() )
{
if( seg->GetNet() == aNetCode )
{
seg->Draw( am_canvas, DC, draw_mode );
}
}
}
/**
* Compute and update the net_codes for PADS et and equipots (.m_NetCode member)
* net_codes are >= 1 (net_code = 0 means not connected)
* Update the net buffer
* Must be called after editing pads (netname, or deleting) or after read a netlist
* set to 1 flag NET_CODE_OK of m_Pcb->m_Status_Pcb;
* m_Pcb->m_NbNodes and m_Pcb->m_NbNets are updated
* Be aware NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname )
* when search a net by its net name does a binary search
* and expects to have a nets list sorted by an alphabetic case sensitive sort
* So do not change Build_Pads_Full_List() which build a sorted list of pads
*/
void NETINFO_LIST::buildListOfNets()
{
D_PAD* pad;
int nodes_count = 0;
// Build the PAD list, sorted by net
buildPadsFullList();
// Restore the initial state of NETINFO_ITEMs
for( NETINFO_LIST::iterator net( begin() ), netEnd( end() ); net != netEnd; ++net )
net->Clear();
// Assign pads to appropriate NETINFO_ITEMs
for( unsigned ii = 0; ii < m_PadsFullList.size(); ii++ )
{
pad = m_PadsFullList[ii];
if( pad->GetNetCode() == NETINFO_LIST::UNCONNECTED ) // pad not connected
continue;
// Add pad to the appropriate list of pads
NETINFO_ITEM* net = pad->GetNet();
// it should not be possible for BOARD_CONNECTED_ITEM to return NULL as a result of GetNet()
wxASSERT( net );
if( net )
net->m_PadInNetList.push_back( pad );
++nodes_count;
}
m_Parent->SetNodeCount( nodes_count );
m_Parent->SynchronizeNetsAndNetClasses( );
m_Parent->m_Status_Pcb |= NET_CODES_OK;
m_Parent->SetAreasNetCodesFromNetNames();
}
bool BOARD_NETLIST_UPDATER::deleteSinglePadNets()
{
int count = 0;
wxString netname;
wxString msg;
D_PAD* pad = NULL;
D_PAD* previouspad = NULL;
// We need the pad list, for next tests.
// padlist is the list of pads, sorted by netname.
m_board->BuildListOfNets();
if( m_isDryRun )
return false;
std::vector<D_PAD*> padlist = m_board->GetPads();
for( unsigned kk = 0; kk < padlist.size(); kk++ )
{
pad = padlist[kk];
if( pad->GetNetname().IsEmpty() )
continue;
if( netname != pad->GetNetname() ) // End of net
{
if( previouspad && count == 1 )
{
// First, see if we have a copper zone attached to this pad.
// If so, this is not really a single pad net
for( int ii = 0; ii < m_board->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = m_board->GetArea( ii );
if( !zone->IsOnCopperLayer() )
continue;
if( zone->GetIsKeepout() )
continue;
if( zone->GetNet() == previouspad->GetNet() )
{
count++;
break;
}
}
if( count == 1 ) // Really one pad, and nothing else
{
msg.Printf( _( "Remove single pad net %s." ),
GetChars( previouspad->GetNetname() ) );
m_reporter->Report( msg, REPORTER::RPT_ACTION );
msg.Printf( _( "Remove single pad net \"%s\" on \"%s\" pad '%s'\n" ),
GetChars( previouspad->GetNetname() ),
GetChars( previouspad->GetParent()->GetReference() ),
GetChars( previouspad->GetPadName() ) );
m_reporter->Report( msg, REPORTER::RPT_ACTION );
previouspad->SetNetCode( NETINFO_LIST::UNCONNECTED );
}
}
netname = pad->GetNetname();
count = 1;
}
else
{
count++;
}
previouspad = pad;
}
// Examine last pad
if( pad && count == 1 )
pad->SetNetCode( NETINFO_LIST::UNCONNECTED );
return true;
}
/**
* Function PlaceCells
* Initialize the matrix routing by setting obstacles for each occupied cell
* a cell set to HOLE is an obstacle for tracks and vias
* a cell set to VIA_IMPOSSIBLE is an obstacle for vias only.
* a cell set to CELL_is_EDGE is a frontier.
* Tracks and vias having the same net code as net_code are skipped
* (htey do not are obstacles)
*
* For single-sided Routing 1:
* BOTTOM side is used, and Route_Layer_BOTTOM = Route_Layer_TOP
*
* If flag == FORCE_PADS: all pads will be put in matrix as obstacles.
*/
void PlaceCells( BOARD* aPcb, int net_code, int flag )
{
int ux0 = 0, uy0 = 0, ux1, uy1, dx, dy;
int marge, via_marge;
LAYER_MSK layerMask;
// use the default NETCLASS?
NETCLASS* nc = aPcb->m_NetClasses.GetDefault();
int trackWidth = nc->GetTrackWidth();
int clearance = nc->GetClearance();
int viaSize = nc->GetViaDiameter();
marge = clearance + (trackWidth / 2);
via_marge = clearance + (viaSize / 2);
// Place PADS on matrix routing:
for( unsigned i = 0; i < aPcb->GetPadCount(); ++i )
{
D_PAD* pad = aPcb->GetPad( i );
if( net_code != pad->GetNet() || (flag & FORCE_PADS) )
{
::PlacePad( pad, HOLE, marge, WRITE_CELL );
}
::PlacePad( pad, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL );
}
// Place outlines of modules on matrix routing, if they are on a copper layer
// or on the edge layer
TRACK tmpSegm( NULL ); // A dummy track used to create segments.
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( BOARD_ITEM* item = module->GraphicalItems(); item; item = item->Next() )
{
switch( item->Type() )
{
case PCB_MODULE_EDGE_T:
{
EDGE_MODULE* edge = (EDGE_MODULE*) item;
tmpSegm.SetLayer( edge->GetLayer() );
if( tmpSegm.GetLayer() == EDGE_N )
tmpSegm.SetLayer( UNDEFINED_LAYER );
tmpSegm.SetStart( edge->GetStart() );
tmpSegm.SetEnd( edge->GetEnd() );
tmpSegm.SetShape( edge->GetShape() );
tmpSegm.SetWidth( edge->GetWidth() );
tmpSegm.m_Param = edge->GetAngle();
tmpSegm.SetNet( -1 );
TraceSegmentPcb( &tmpSegm, HOLE, marge, WRITE_CELL );
TraceSegmentPcb( &tmpSegm, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL );
}
break;
default:
break;
}
}
}
// Place board outlines and texts on copper layers:
for( BOARD_ITEM* item = aPcb->m_Drawings; item; item = item->Next() )
{
switch( item->Type() )
{
case PCB_LINE_T:
{
DRAWSEGMENT* DrawSegm;
int type_cell = HOLE;
DrawSegm = (DRAWSEGMENT*) item;
tmpSegm.SetLayer( DrawSegm->GetLayer() );
if( DrawSegm->GetLayer() == EDGE_N )
{
tmpSegm.SetLayer( UNDEFINED_LAYER );
type_cell |= CELL_is_EDGE;
}
tmpSegm.SetStart( DrawSegm->GetStart() );
tmpSegm.SetEnd( DrawSegm->GetEnd() );
tmpSegm.SetShape( DrawSegm->GetShape() );
tmpSegm.SetWidth( DrawSegm->GetWidth() );
tmpSegm.m_Param = DrawSegm->GetAngle();
tmpSegm.SetNet( -1 );
TraceSegmentPcb( &tmpSegm, type_cell, marge, WRITE_CELL );
}
break;
case PCB_TEXT_T:
{
TEXTE_PCB* PtText;
PtText = (TEXTE_PCB*) item;
if( PtText->GetText().Length() == 0 )
break;
EDA_RECT textbox = PtText->GetTextBox( -1 );
ux0 = textbox.GetX();
uy0 = textbox.GetY();
dx = textbox.GetWidth();
dy = textbox.GetHeight();
/* Put bounding box (rectangle) on matrix */
dx /= 2;
dy /= 2;
ux1 = ux0 + dx;
uy1 = uy0 + dy;
ux0 -= dx;
uy0 -= dy;
layerMask = GetLayerMask( PtText->GetLayer() );
TraceFilledRectangle( ux0 - marge, uy0 - marge, ux1 + marge,
uy1 + marge, PtText->GetOrientation(),
layerMask, HOLE, WRITE_CELL );
TraceFilledRectangle( ux0 - via_marge, uy0 - via_marge,
ux1 + via_marge, uy1 + via_marge,
PtText->GetOrientation(),
layerMask, VIA_IMPOSSIBLE, WRITE_OR_CELL );
}
break;
default:
break;
}
}
/* Put tracks and vias on matrix */
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( net_code == track->GetNet() )
continue;
TraceSegmentPcb( track, HOLE, marge, WRITE_CELL );
TraceSegmentPcb( track, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL );
}
}
/*
* This function starts a new track segment.
* If a new track segment is in progress, ends this current new segment,
* and created a new one.
*/
TRACK* PCB_EDIT_FRAME::Begin_Route( TRACK* aTrack, wxDC* aDC )
{
TRACK* TrackOnStartPoint = NULL;
int layerMask = GetLayerMask( GetScreen()->m_Active_Layer );
BOARD_CONNECTED_ITEM* LockPoint;
wxPoint pos = GetScreen()->GetCrossHairPosition();
if( aTrack == NULL ) // Starting a new track segment
{
m_canvas->SetMouseCapture( ShowNewTrackWhenMovingCursor, Abort_Create_Track );
// Prepare the undo command info
s_ItemsListPicker.ClearListAndDeleteItems(); // Should not be necessary, but...
GetBoard()->PushHighLight();
// erase old highlight
if( GetBoard()->IsHighLightNetON() )
HighLight( aDC );
g_CurrentTrackList.PushBack( new TRACK( GetBoard() ) );
g_CurrentTrackSegment->SetFlags( IS_NEW );
GetBoard()->SetHighLightNet( 0 );
// Search for a starting point of the new track, a track or pad
LockPoint = GetBoard()->GetLockPoint( pos, layerMask );
D_PAD* pad = NULL;
if( LockPoint ) // An item (pad or track) is found
{
if( LockPoint->Type() == PCB_PAD_T )
{
pad = (D_PAD*) LockPoint;
// A pad is found: put the starting point on pad center
pos = pad->GetPosition();
GetBoard()->SetHighLightNet( pad->GetNet() );
}
else // A track segment is found
{
TrackOnStartPoint = (TRACK*) LockPoint;
GetBoard()->SetHighLightNet( TrackOnStartPoint->GetNet() );
GetBoard()->CreateLockPoint( pos, TrackOnStartPoint, &s_ItemsListPicker );
}
}
else
{
// Not a starting point, but a filled zone area can exist. This is also a
// good starting point.
ZONE_CONTAINER* zone;
zone = GetBoard()->HitTestForAnyFilledArea( pos, GetScreen()-> m_Active_Layer );
if( zone )
GetBoard()->SetHighLightNet( zone->GetNet() );
}
D( g_CurrentTrackList.VerifyListIntegrity() );
BuildAirWiresTargetsList( LockPoint, wxPoint( 0, 0 ), true );
D( g_CurrentTrackList.VerifyListIntegrity() );
GetBoard()->HighLightON();
GetBoard()->DrawHighLight( m_canvas, aDC, GetBoard()->GetHighLightNetCode() );
// Display info about track Net class, and init track and vias sizes:
g_CurrentTrackSegment->SetNet( GetBoard()->GetHighLightNetCode() );
GetBoard()->SetCurrentNetClass( g_CurrentTrackSegment->GetNetClassName() );
g_CurrentTrackSegment->SetLayer( GetScreen()->m_Active_Layer );
g_CurrentTrackSegment->SetWidth( GetBoard()->GetCurrentTrackWidth() );
if( GetBoard()->GetDesignSettings().m_UseConnectedTrackWidth )
{
if( TrackOnStartPoint && TrackOnStartPoint->Type() == PCB_TRACE_T )
g_CurrentTrackSegment->SetWidth( TrackOnStartPoint->GetWidth());
}
g_CurrentTrackSegment->SetStart( pos );
g_CurrentTrackSegment->SetEnd( pos );
if( pad )
{
g_CurrentTrackSegment->m_PadsConnected.push_back( pad );
// Useful to display track length, if the pad has a die length:
g_CurrentTrackSegment->SetState( BEGIN_ONPAD, ON );
g_CurrentTrackSegment->start = pad;
}
if( g_TwoSegmentTrackBuild )
{
// Create 2nd segment
g_CurrentTrackList.PushBack( (TRACK*)g_CurrentTrackSegment->Clone() );
D( g_CurrentTrackList.VerifyListIntegrity(); );
g_CurrentTrackSegment->start = g_FirstTrackSegment;
g_FirstTrackSegment->end = g_CurrentTrackSegment;
g_FirstTrackSegment->SetState( BEGIN_ONPAD | END_ONPAD, OFF );
}
void ZONE_CONTAINER::TestForCopperIslandAndRemoveInsulatedIslands( BOARD* aPcb )
{
if( m_FilledPolysList.GetCornersCount() == 0 )
return;
// Build a list of points connected to the net:
// list of coordinates of pads and vias on this layer and on this net.
std::vector <wxPoint> listPointsCandidates;
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad != NULL; pad = pad->Next() )
{
if( !pad->IsOnLayer( GetLayer() ) )
continue;
if( pad->GetNet() != GetNet() )
continue;
listPointsCandidates.push_back( pad->GetPosition() );
}
}
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( !track->IsOnLayer( GetLayer() ) )
continue;
if( track->GetNet() != GetNet() )
continue;
listPointsCandidates.push_back( track->GetStart() );
if( track->Type() != PCB_VIA_T )
listPointsCandidates.push_back( track->GetEnd() );
}
// test if a point is inside
unsigned indexstart = 0, indexend;
bool connected = false;
for( indexend = 0; indexend < m_FilledPolysList.GetCornersCount(); indexend++ )
{
if( m_FilledPolysList[indexend].end_contour ) // end of a filled sub-area found
{
EDA_RECT bbox = CalculateSubAreaBoundaryBox( indexstart, indexend );
for( unsigned ic = 0; ic < listPointsCandidates.size(); ic++ )
{
// test if this area is connected to a board item:
wxPoint pos = listPointsCandidates[ic];
if( !bbox.Contains( pos ) )
continue;
if( TestPointInsidePolygon( m_FilledPolysList, indexstart, indexend,
pos.x, pos.y ) )
{
connected = true;
break;
}
}
if( connected ) // this polygon is connected: analyse next polygon
{
indexstart = indexend + 1; // indexstart points the first point of the next polygon
connected = false;
}
else // Not connected: remove this polygon
{
m_FilledPolysList.DeleteCorners( indexstart, indexend );
indexend = indexstart; /* indexstart points the first point of the next polygon
* because the current poly is removed */
}
}
}
}
MODULE::MODULE( const MODULE& aModule ) :
BOARD_ITEM( aModule )
{
m_Pos = aModule.m_Pos;
m_fpid = aModule.m_fpid;
m_Layer = aModule.m_Layer;
m_Attributs = aModule.m_Attributs;
m_ModuleStatus = aModule.m_ModuleStatus;
m_Orient = aModule.m_Orient;
m_BoundaryBox = aModule.m_BoundaryBox;
m_CntRot90 = aModule.m_CntRot90;
m_CntRot180 = aModule.m_CntRot180;
m_LastEditTime = aModule.m_LastEditTime;
m_Link = aModule.m_Link;
m_Path = aModule.m_Path; //is this correct behavior?
m_LocalClearance = aModule.m_LocalClearance;
m_LocalSolderMaskMargin = aModule.m_LocalSolderMaskMargin;
m_LocalSolderPasteMargin = aModule.m_LocalSolderPasteMargin;
m_LocalSolderPasteMarginRatio = aModule.m_LocalSolderPasteMarginRatio;
m_ZoneConnection = aModule.m_ZoneConnection;
m_ThermalWidth = aModule.m_ThermalWidth;
m_ThermalGap = aModule.m_ThermalGap;
// Copy reference and value.
m_Reference = new TEXTE_MODULE( *aModule.m_Reference );
m_Reference->SetParent( this );
m_Value = new TEXTE_MODULE( *aModule.m_Value );
m_Value->SetParent( this );
// Copy auxiliary data: Pads
for( D_PAD* pad = aModule.m_Pads; pad; pad = pad->Next() )
{
D_PAD* newpad = new D_PAD( *pad );
assert( newpad->GetNet() == pad->GetNet() );
newpad->SetParent( this );
m_Pads.PushBack( newpad );
}
// Copy auxiliary data: Drawings
for( BOARD_ITEM* item = aModule.m_Drawings; item; item = item->Next() )
{
BOARD_ITEM* newItem;
switch( item->Type() )
{
case PCB_MODULE_TEXT_T:
case PCB_MODULE_EDGE_T:
newItem = static_cast<BOARD_ITEM*>( item->Clone() );
newItem->SetParent( this );
m_Drawings.PushBack( newItem );
break;
default:
wxLogMessage( wxT( "MODULE::Copy() Internal Err: unknown type" ) );
break;
}
}
// Copy auxiliary data: 3D_Drawings info
for( S3D_MASTER* item = aModule.m_3D_Drawings; item; item = item->Next() )
{
if( item->GetShape3DName().IsEmpty() ) // do not copy empty shapes.
continue;
S3D_MASTER* t3d = new S3D_MASTER( this );
t3d->Copy( item );
m_3D_Drawings.PushBack( t3d );
}
// Ensure there is at least one item in m_3D_Drawings.
if( m_3D_Drawings.GetCount() == 0 )
m_3D_Drawings.PushBack( new S3D_MASTER( this ) ); // push a void item
m_Doc = aModule.m_Doc;
m_KeyWord = aModule.m_KeyWord;
m_arflag = 0;
// Ensure auxiliary data is up to date
CalculateBoundingBox();
m_initial_comments = aModule.m_initial_comments ?
new wxArrayString( *aModule.m_initial_comments ) : 0;
}
/* init board, route traces*/
void PCB_EDIT_FRAME::Autoroute( wxDC* DC, int mode )
{
int start, stop;
MODULE* Module = NULL;
D_PAD* Pad = NULL;
int autoroute_net_code = -1;
wxString msg;
if( GetBoard()->GetCopperLayerCount() > 1 )
{
Route_Layer_TOP = GetScreen()->m_Route_Layer_TOP;
Route_Layer_BOTTOM = GetScreen()->m_Route_Layer_BOTTOM;
}
else
{
Route_Layer_TOP = Route_Layer_BOTTOM = LAYER_N_BACK;
}
switch( mode )
{
case ROUTE_NET:
if( GetScreen()->GetCurItem() )
{
switch( GetScreen()->GetCurItem()->Type() )
{
case PCB_PAD_T:
Pad = (D_PAD*) GetScreen()->GetCurItem();
autoroute_net_code = Pad->GetNet();
break;
default:
break;
}
}
if( autoroute_net_code <= 0 )
{
wxMessageBox( _( "Net not selected" ) );
return;
}
break;
case ROUTE_MODULE:
Module = (MODULE*) GetScreen()->GetCurItem();
if( (Module == NULL) || (Module->Type() != PCB_MODULE_T) )
{
wxMessageBox( _( "Module not selected" ) );
return;
}
break;
case ROUTE_PAD:
Pad = (D_PAD*) GetScreen()->GetCurItem();
if( (Pad == NULL) || (Pad->Type() != PCB_PAD_T) )
{
wxMessageBox( _( "Pad not selected" ) );
return;
}
break;
}
if( (GetBoard()->m_Status_Pcb & LISTE_RATSNEST_ITEM_OK ) == 0 )
Compile_Ratsnest( DC, true );
/* Set the flag on the ratsnest to CH_ROUTE_REQ. */
for( unsigned ii = 0; ii < GetBoard()->GetRatsnestsCount(); ii++ )
{
RATSNEST_ITEM* ptmp = &GetBoard()->m_FullRatsnest[ii];
ptmp->m_Status &= ~CH_ROUTE_REQ;
switch( mode )
{
case ROUTE_ALL:
ptmp->m_Status |= CH_ROUTE_REQ;
break;
case ROUTE_NET:
if( autoroute_net_code == ptmp->GetNet() )
ptmp->m_Status |= CH_ROUTE_REQ;
break;
case ROUTE_MODULE:
{
D_PAD* pt_pad = (D_PAD*) Module->m_Pads;
for( ; pt_pad != NULL; pt_pad = pt_pad->Next() )
{
if( ptmp->m_PadStart == pt_pad )
ptmp->m_Status |= CH_ROUTE_REQ;
if( ptmp->m_PadEnd == pt_pad )
ptmp->m_Status |= CH_ROUTE_REQ;
}
break;
}
case ROUTE_PAD:
if( ( ptmp->m_PadStart == Pad ) || ( ptmp->m_PadEnd == Pad ) )
ptmp->m_Status |= CH_ROUTE_REQ;
break;
}
}
start = time( NULL );
/* Calculation of no fixed routing to 5 mils and more. */
RoutingMatrix.m_GridRouting = (int)GetScreen()->GetGridSize().x;
if( RoutingMatrix.m_GridRouting < (5*IU_PER_MILS) )
RoutingMatrix.m_GridRouting = 5*IU_PER_MILS;
/* Calculated ncol and nrow, matrix size for routing. */
RoutingMatrix.ComputeMatrixSize( GetBoard() );
m_messagePanel->EraseMsgBox();
/* Map the board */
RoutingMatrix.m_RoutingLayersCount = 1;
if( Route_Layer_TOP != Route_Layer_BOTTOM )
RoutingMatrix.m_RoutingLayersCount = 2;
if( RoutingMatrix.InitRoutingMatrix() < 0 )
{
wxMessageBox( _( "No memory for autorouting" ) );
RoutingMatrix.UnInitRoutingMatrix(); /* Free memory. */
return;
}
SetStatusText( _( "Place Cells" ) );
PlaceCells( GetBoard(), -1, FORCE_PADS );
/* Construction of the track list for router. */
RoutingMatrix.m_RouteCount = Build_Work( GetBoard() );
// DisplayRoutingMatrix( m_canvas, DC );
Solve( DC, RoutingMatrix.m_RoutingLayersCount );
/* Free memory. */
FreeQueue();
InitWork(); /* Free memory for the list of router connections. */
RoutingMatrix.UnInitRoutingMatrix();
stop = time( NULL ) - start;
msg.Printf( wxT( "time = %d second%s" ), stop, ( stop == 1 ) ? wxT( "" ) : wxT( "s" ) );
SetStatusText( msg );
}
bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
{
TRACK* track;
wxPoint delta; // lenght on X and Y axis of segments
LAYER_MSK layerMask;
int net_code_ref;
wxPoint shape_pos;
NETCLASS* netclass = aRefSeg->GetNetClass();
/* In order to make some calculations more easier or faster,
* pads and tracks coordinates will be made relative to the reference segment origin
*/
wxPoint origin = aRefSeg->GetStart(); // origin will be the origin of other coordinates
m_segmEnd = delta = aRefSeg->GetEnd() - origin;
m_segmAngle = 0;
layerMask = aRefSeg->GetLayerMask();
net_code_ref = aRefSeg->GetNet();
// Phase 0 : Test vias
if( aRefSeg->Type() == PCB_VIA_T )
{
// test if the via size is smaller than minimum
if( aRefSeg->GetShape() == VIA_MICROVIA )
{
if( aRefSeg->GetWidth() < netclass->GetuViaMinDiameter() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_MICROVIA, m_currentMarker );
return false;
}
}
else
{
if( aRefSeg->GetWidth() < netclass->GetViaMinDiameter() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_VIA, m_currentMarker );
return false;
}
}
// test if via's hole is bigger than its diameter
// This test is necessary since the via hole size and width can be modified
// and a default via hole can be bigger than some vias sizes
if( aRefSeg->GetDrillValue() > aRefSeg->GetWidth() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_VIA_HOLE_BIGGER, m_currentMarker );
return false;
}
// For microvias: test if they are blind vias and only between 2 layers
// because they are used for very small drill size and are drill by laser
// and **only one layer** can be drilled
if( aRefSeg->GetShape() == VIA_MICROVIA )
{
LAYER_NUM layer1, layer2;
bool err = true;
( (SEGVIA*) aRefSeg )->ReturnLayerPair( &layer1, &layer2 );
if( layer1 > layer2 )
EXCHG( layer1, layer2 );
// test:
if( layer1 == LAYER_N_BACK && layer2 == LAYER_N_2 )
err = false;
if( layer1 == (m_pcb->GetDesignSettings().GetCopperLayerCount() - 2 )
&& layer2 == LAYER_N_FRONT )
err = false;
if( err )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_MICRO_VIA_INCORRECT_LAYER_PAIR, m_currentMarker );
return false;
}
}
}
else // This is a track segment
{
if( aRefSeg->GetWidth() < netclass->GetTrackMinWidth() )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_TRACK_WIDTH, m_currentMarker );
return false;
}
}
// for a non horizontal or vertical segment Compute the segment angle
// in tenths of degrees and its length
if( delta.x || delta.y )
{
// Compute the segment angle in 0,1 degrees
m_segmAngle = ArcTangente( delta.y, delta.x );
// Compute the segment length: we build an equivalent rotated segment,
// this segment is horizontal, therefore dx = length
RotatePoint( &delta, m_segmAngle ); // delta.x = length, delta.y = 0
}
m_segmLength = delta.x;
/******************************************/
/* Phase 1 : test DRC track to pads : */
/******************************************/
/* Use a dummy pad to test DRC tracks versus holes, for pads not on all copper layers
* but having a hole
* This dummy pad has the size and shape of the hole
* to test tracks to pad hole DRC, using checkClearanceSegmToPad test function.
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( m_pcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
dummypad.SetLayerMask( ALL_CU_LAYERS ); // Ensure the hole is on all layers
// Compute the min distance to pads
if( testPads )
{
for( unsigned ii = 0; ii<m_pcb->GetPadCount(); ++ii )
{
D_PAD* pad = m_pcb->GetPad( ii );
/* No problem if pads are on an other layer,
* But if a drill hole exists (a pad on a single layer can have a hole!)
* we must test the hole
*/
if( (pad->GetLayerMask() & layerMask ) == 0 )
{
/* We must test the pad hole. In order to use the function
* checkClearanceSegmToPad(),a pseudo pad is used, with a shape and a
* size like the hole
*/
if( pad->GetDrillSize().x == 0 )
continue;
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetPosition( pad->GetPosition() );
dummypad.SetShape( pad->GetDrillShape() );
dummypad.SetOrientation( pad->GetOrientation() );
m_padToTestPos = dummypad.GetPosition() - origin;
if( !checkClearanceSegmToPad( &dummypad, aRefSeg->GetWidth(),
netclass->GetClearance() ) )
{
m_currentMarker = fillMarker( aRefSeg, pad,
DRCE_TRACK_NEAR_THROUGH_HOLE, m_currentMarker );
return false;
}
continue;
}
// The pad must be in a net (i.e pt_pad->GetNet() != 0 )
// but no problem if the pad netcode is the current netcode (same net)
if( pad->GetNet() // the pad must be connected
&& net_code_ref == pad->GetNet() ) // the pad net is the same as current net -> Ok
continue;
// DRC for the pad
shape_pos = pad->ReturnShapePos();
m_padToTestPos = shape_pos - origin;
if( !checkClearanceSegmToPad( pad, aRefSeg->GetWidth(), aRefSeg->GetClearance( pad ) ) )
{
m_currentMarker = fillMarker( aRefSeg, pad,
DRCE_TRACK_NEAR_PAD, m_currentMarker );
return false;
}
}
}
/***********************************************/
/* Phase 2: test DRC with other track segments */
/***********************************************/
// At this point the reference segment is the X axis
// Test the reference segment with other track segments
wxPoint segStartPoint;
wxPoint segEndPoint;
for( track = aStart; track; track = track->Next() )
{
// No problem if segments have the same net code:
if( net_code_ref == track->GetNet() )
continue;
// No problem if segment are on different layers :
if( ( layerMask & track->GetLayerMask() ) == 0 )
continue;
// the minimum distance = clearance plus half the reference track
// width plus half the other track's width
int w_dist = aRefSeg->GetClearance( track );
w_dist += (aRefSeg->GetWidth() + track->GetWidth()) / 2;
// If the reference segment is a via, we test it here
if( aRefSeg->Type() == PCB_VIA_T )
{
delta = track->GetEnd() - track->GetStart();
segStartPoint = aRefSeg->GetStart() - track->GetStart();
if( track->Type() == PCB_VIA_T )
{
// Test distance between two vias, i.e. two circles, trivial case
if( EuclideanNorm( segStartPoint ) < w_dist )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_VIA_NEAR_VIA, m_currentMarker );
return false;
}
}
else // test via to segment
{
// Compute l'angle du segment a tester;
double angle = ArcTangente( delta.y, delta.x );
// Compute new coordinates ( the segment become horizontal)
RotatePoint( &delta, angle );
RotatePoint( &segStartPoint, angle );
if( !checkMarginToCircle( segStartPoint, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( track, aRefSeg,
DRCE_VIA_NEAR_TRACK, m_currentMarker );
return false;
}
}
continue;
}
/* We compute segStartPoint, segEndPoint = starting and ending point coordinates for
* the segment to test in the new axis : the new X axis is the
* reference segment. We must translate and rotate the segment to test
*/
segStartPoint = track->GetStart() - origin;
segEndPoint = track->GetEnd() - origin;
RotatePoint( &segStartPoint, m_segmAngle );
RotatePoint( &segEndPoint, m_segmAngle );
if( track->Type() == PCB_VIA_T )
{
if( checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
continue;
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_NEAR_VIA, m_currentMarker );
return false;
}
/* We have changed axis:
* the reference segment is Horizontal.
* 3 cases : the segment to test can be parallel, perpendicular or have an other direction
*/
if( segStartPoint.y == segEndPoint.y ) // parallel segments
{
if( abs( segStartPoint.y ) >= w_dist )
continue;
// Ensure segStartPoint.x <= segEndPoint.x
if( segStartPoint.x > segEndPoint.x )
EXCHG( segStartPoint.x, segEndPoint.x );
if( segStartPoint.x > (-w_dist) && segStartPoint.x < (m_segmLength + w_dist) ) /* possible error drc */
{
// the start point is inside the reference range
// X........
// O--REF--+
// Fine test : we consider the rounded shape of each end of the track segment:
if( segStartPoint.x >= 0 && segStartPoint.x <= m_segmLength )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS1, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS2, m_currentMarker );
return false;
}
}
if( segEndPoint.x > (-w_dist) && segEndPoint.x < (m_segmLength + w_dist) )
{
// the end point is inside the reference range
// .....X
// O--REF--+
// Fine test : we consider the rounded shape of the ends
if( segEndPoint.x >= 0 && segEndPoint.x <= m_segmLength )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS3, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segEndPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS4, m_currentMarker );
return false;
}
}
if( segStartPoint.x <=0 && segEndPoint.x >= 0 )
{
// the segment straddles the reference range (this actually only
// checks if it straddles the origin, because the other cases where already
// handled)
// X.............X
// O--REF--+
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_SEGMENTS_TOO_CLOSE, m_currentMarker );
return false;
}
}
else if( segStartPoint.x == segEndPoint.x ) // perpendicular segments
{
if( ( segStartPoint.x <= (-w_dist) ) || ( segStartPoint.x >= (m_segmLength + w_dist) ) )
continue;
// Test if segments are crossing
if( segStartPoint.y > segEndPoint.y )
EXCHG( segStartPoint.y, segEndPoint.y );
if( (segStartPoint.y < 0) && (segEndPoint.y > 0) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACKS_CROSSING, m_currentMarker );
return false;
}
// At this point the drc error is due to an end near a reference segm end
if( !checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM1, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segEndPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM2, m_currentMarker );
return false;
}
}
else // segments quelconques entre eux
{
// calcul de la "surface de securite du segment de reference
// First rought 'and fast) test : the track segment is like a rectangle
m_xcliplo = m_ycliplo = -w_dist;
m_xcliphi = m_segmLength + w_dist;
m_ycliphi = w_dist;
// A fine test is needed because a serment is not exactly a
// rectangle, it has rounded ends
if( !checkLine( segStartPoint, segEndPoint ) )
{
/* 2eme passe : the track has rounded ends.
* we must a fine test for each rounded end and the
* rectangular zone
*/
m_xcliplo = 0;
m_xcliphi = m_segmLength;
if( !checkLine( segStartPoint, segEndPoint ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM3, m_currentMarker );
return false;
}
else // The drc error is due to the starting or the ending point of the reference segment
{
// Test the starting and the ending point
segStartPoint = track->GetStart();
segEndPoint = track->GetEnd();
delta = segEndPoint - segStartPoint;
// Compute the segment orientation (angle) en 0,1 degre
double angle = ArcTangente( delta.y, delta.x );
// Compute the segment lenght: delta.x = lenght after rotation
RotatePoint( &delta, angle );
/* Comute the reference segment coordinates relatives to a
* X axis = current tested segment
*/
wxPoint relStartPos = aRefSeg->GetStart() - segStartPoint;
wxPoint relEndPos = aRefSeg->GetEnd() - segStartPoint;
RotatePoint( &relStartPos, angle );
RotatePoint( &relEndPos, angle );
if( !checkMarginToCircle( relStartPos, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM4, m_currentMarker );
return false;
}
if( !checkMarginToCircle( relEndPos, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM5, m_currentMarker );
return false;
}
}
}
}
}
return true;
}
