//------------------------------------------------------------------------
// ContainCheckIndir: Determine whether operands of an indir should be contained.
//
// Arguments:
// indirNode - The indirection node of interest
//
// Notes:
// This is called for both store and load indirections.
//
// Return Value:
// None.
//
void Lowering::ContainCheckIndir(GenTreeIndir* indirNode)
{
// If this is the rhs of a block copy it will be handled when we handle the store.
if (indirNode->TypeGet() == TYP_STRUCT)
{
return;
}
#ifdef FEATURE_SIMD
// If indirTree is of TYP_SIMD12, don't mark addr as contained
// so that it always get computed to a register. This would
// mean codegen side logic doesn't need to handle all possible
// addr expressions that could be contained.
//
// TODO-ARM64-CQ: handle other addr mode expressions that could be marked
// as contained.
if (indirNode->TypeGet() == TYP_SIMD12)
{
return;
}
#endif // FEATURE_SIMD
GenTree* addr = indirNode->Addr();
bool makeContained = true;
if ((addr->OperGet() == GT_LEA) && IsSafeToContainMem(indirNode, addr))
{
GenTreeAddrMode* lea = addr->AsAddrMode();
GenTree* base = lea->Base();
GenTree* index = lea->Index();
int cns = lea->Offset();
#ifdef _TARGET_ARM_
// ARM floating-point load/store doesn't support a form similar to integer
// ldr Rdst, [Rbase + Roffset] with offset in a register. The only supported
// form is vldr Rdst, [Rbase + imm] with a more limited constraint on the imm.
if (lea->HasIndex() || !emitter::emitIns_valid_imm_for_vldst_offset(cns))
{
if (indirNode->OperGet() == GT_STOREIND)
{
if (varTypeIsFloating(indirNode->AsStoreInd()->Data()))
{
makeContained = false;
}
}
else if (indirNode->OperGet() == GT_IND)
{
if (varTypeIsFloating(indirNode))
{
makeContained = false;
}
}
}
#endif
if (makeContained)
{
MakeSrcContained(indirNode, addr);
}
}
}
//------------------------------------------------------------------------
// ContainCheckIndir: Determine whether operands of an indir should be contained.
//
// Arguments:
// indirNode - The indirection node of interest
//
// Notes:
// This is called for both store and load indirections.
//
// Return Value:
// None.
//
void Lowering::ContainCheckIndir(GenTreeIndir* indirNode)
{
// If this is the rhs of a block copy it will be handled when we handle the store.
if (indirNode->TypeGet() == TYP_STRUCT)
{
return;
}
GenTree* addr = indirNode->Addr();
bool makeContained = true;
if ((addr->OperGet() == GT_LEA) && IsSafeToContainMem(indirNode, addr))
{
GenTreeAddrMode* lea = addr->AsAddrMode();
GenTree* base = lea->Base();
GenTree* index = lea->Index();
int cns = lea->Offset();
#ifdef _TARGET_ARM_
// ARM floating-point load/store doesn't support a form similar to integer
// ldr Rdst, [Rbase + Roffset] with offset in a register. The only supported
// form is vldr Rdst, [Rbase + imm] with a more limited constraint on the imm.
if (lea->HasIndex() || !emitter::emitIns_valid_imm_for_vldst_offset(cns))
{
if (indirNode->OperGet() == GT_STOREIND)
{
if (varTypeIsFloating(indirNode->AsStoreInd()->Data()))
{
makeContained = false;
}
}
else if (indirNode->OperGet() == GT_IND)
{
if (varTypeIsFloating(indirNode))
{
makeContained = false;
}
}
}
#endif
if (makeContained)
{
MakeSrcContained(indirNode, addr);
}
}
}
//------------------------------------------------------------------------
// TreeNodeInfoInitIndir: Specify register requirements for address expression
// of an indirection operation.
//
// Arguments:
// indirTree - GT_IND, GT_STOREIND, block node or GT_NULLCHECK gentree node
//
void Lowering::TreeNodeInfoInitIndir(GenTreeIndir* indirTree)
{
ContainCheckIndir(indirTree);
// If this is the rhs of a block copy (i.e. non-enregisterable struct),
// it has no register requirements.
if (indirTree->TypeGet() == TYP_STRUCT)
{
return;
}
TreeNodeInfo* info = &(indirTree->gtLsraInfo);
bool isStore = (indirTree->gtOper == GT_STOREIND);
info->srcCount = GetIndirSourceCount(indirTree);
GenTree* addr = indirTree->Addr();
GenTree* index = nullptr;
unsigned cns = 0;
#ifdef _TARGET_ARM_
// Unaligned loads/stores for floating point values must first be loaded into integer register(s)
if (indirTree->gtFlags & GTF_IND_UNALIGNED)
{
var_types type = TYP_UNDEF;
if (indirTree->OperGet() == GT_STOREIND)
{
type = indirTree->AsStoreInd()->Data()->TypeGet();
}
else if (indirTree->OperGet() == GT_IND)
{
type = indirTree->TypeGet();
}
if (type == TYP_FLOAT)
{
info->internalIntCount = 1;
}
else if (type == TYP_DOUBLE)
{
info->internalIntCount = 2;
}
}
#endif
if (addr->isContained())
{
assert(addr->OperGet() == GT_LEA);
GenTreeAddrMode* lea = addr->AsAddrMode();
index = lea->Index();
cns = lea->gtOffset;
// On ARM we may need a single internal register
// (when both conditions are true then we still only need a single internal register)
if ((index != nullptr) && (cns != 0))
{
// ARM does not support both Index and offset so we need an internal register
info->internalIntCount++;
}
else if (!emitter::emitIns_valid_imm_for_ldst_offset(cns, emitTypeSize(indirTree)))
{
// This offset can't be contained in the ldr/str instruction, so we need an internal register
info->internalIntCount++;
}
}
}