C++ (Cpp) HSim__s6::checkTopLevelPortsConstrainted示例

示例#1

文件： xsimtestbench_arch.cpp 项目： hitwow/CPU-VHDL

    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        HSim__s6 * topvh = 0;
        extern HSim__s6 * createWork_w_alublock_testbench_arch(const char*);
        topvh = createWork_w_alublock_testbench_arch("w_alublock");
        topvh->constructPorts();
        topvh->checkTopLevelPortsConstrainted();
        topvh->vhdlArchImplement();
        topvh->architectureInstantiate(cfgvh);
        addChild(topvh);
        return cfgvh;
}

示例#2

文件： xsimbehavior.cpp 项目： heshuimu/EECS645FALL2015HW2

    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        (*cfgvh).registerFuseLibList("");

        HSim__s6 * topvh = 0;
        extern HSim__s6 * createWork_q2vhdlkmaptestbench_vhd_behavior(const char*);
        topvh = createWork_q2vhdlkmaptestbench_vhd_behavior("Q2VHDLKmapTestBench_vhd");
        topvh->constructPorts();
        topvh->checkTopLevelPortsConstrainted();
        topvh->vhdlArchImplement();
        topvh->architectureInstantiate(cfgvh);
        addChild(topvh);
        return cfgvh;
}

示例#3

文件： xsimtestbench_arch.cpp 项目： erik1o6/VHDL

    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        (*cfgvh).registerFuseLibList("unisims_ver");

        HSim__s6 * topvh = 0;
        extern HSim__s6 * createWork_test1_testbench_arch(const char*);
        topvh = createWork_test1_testbench_arch("test1");
        topvh->constructPorts();
        topvh->checkTopLevelPortsConstrainted();
        topvh->vhdlArchImplement();
        topvh->architectureInstantiate(cfgvh);
        addChild(topvh);
        return cfgvh;
}