示例#1
0
void DEX_REGION::process_simply(OUT PRNO2UINT & prno2v, UINT param_num,
								UINT vregnum, DEX2IR & d2ir, UINT2PR * v2pr,
								IN PRNO2UINT * pr2v, TYIDR * tr)
{
	LOG("\t\t Invoke DEX_REGION::process_simply '%s'", get_ru_name());
	if (get_ir_list() == NULL) { return ; }
	OPT_CTX oc;
	OPTC_show_comp_time(oc) = g_show_comp_time;

	CHAR const* ru_name = get_ru_name();

	construct_ir_bb_list();

	IS_TRUE0(verify_ir_and_bb(get_bb_list(), get_dm()));

	RU_ana(this)->m_ir_list = NULL; //All IRs have been moved to each IR_BB.

	IR_CFG * cfg = init_cfg(oc);
	cfg->loop_analysis(oc);

	PASS_MGR * pm = new_pass_mgr();
	OPTC_pass_mgr(oc) = pm; //record pass manager.

	if (g_do_ssa && OPTC_pass_mgr(oc) != NULL) {
		//Convert program to ssa form.
		IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)OPTC_pass_mgr(oc)->
									register_opt(OPT_SSA_MGR);
		IS_TRUE0(ssamgr);
		ssamgr->construction(oc, this);
	}

	init_aa(oc);

	init_du(oc);

	IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)pm->query_opt(OPT_SSA_MGR);
	if (ssamgr != NULL && ssamgr->is_ssa_construct()) {
		//Destruct ssa form.
		ssamgr->destruction_in_bblist_order();
	}

	delete pm;

	OPTC_pass_mgr(oc) = NULL;

	#if 1
	//Do not allocate register.
	prno2v.clean();
	prno2v.copy(*d2ir.get_pr2v_map());
	return;
	#else
	//Allocate register.
	RA ra(this, tr, param_num, vregnum, v2pr, pr2v, &m_var2pr);
	LOG("\t\tdo DEX Register Allcation for '%s'", ru_name);
	ra.perform(oc);
	update_ra_res(ra, prno2v);
	#endif
}
示例#2
0
bool DEX_REGION::high_process(OPT_CTX & oc)
{
	CHAR const* ru_name = get_ru_name();
	g_indent = 0;
	SIMP_CTX simp;
	SIMP_if(&simp) = 1;
	SIMP_do_loop(&simp) = 1;
	SIMP_do_while(&simp) = 1;
	SIMP_while_do(&simp) = 1;
	SIMP_switch(&simp) = 0;
	SIMP_break(&simp) = 1;
	SIMP_continue(&simp) = 1;

	RU_ana(this)->m_ir_list = simplify_stmt_list(get_ir_list(), &simp);

	IS_TRUE0(verify_simp(get_ir_list(), simp));
	IS_TRUE0(verify_irs(get_ir_list(), NULL, get_dm()));

	construct_ir_bb_list();

	IS_TRUE0(verify_ir_and_bb(get_bb_list(), get_dm()));

	RU_ana(this)->m_ir_list = NULL; //All IRs have been moved to each IR_BB.

	IS_TRUE0(g_do_cfg && g_do_aa && g_do_du_ana && g_do_cdg);

	IR_CFG * cfg = init_cfg(oc);
	cfg->loop_analysis(oc);

	if (g_do_ssa && OPTC_pass_mgr(oc) != NULL) {
		IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)OPTC_pass_mgr(oc)->
									register_opt(OPT_SSA_MGR);
		IS_TRUE0(ssamgr);
		ssamgr->construction(oc, this);
	}

	init_aa(oc);

	init_du(oc);

	if (g_opt_level == NO_OPT) {
		return false;
	}
	return true;
}